SiC MOSFET Trench Gate Structure for On-Resistance Reduction
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Solution Overview
Problem
Existing semiconductor devices, particularly MOSFETs, face challenges in reducing on-resistance while maintaining breakdown voltage and short-circuit withstand capability, especially due to the short channel effect and punch-through issues associated with silicon carbide materials.
Innovation Solution
A silicon carbide-based MOSFET with a trench gate structure and a p+-type high concentration region is implemented, featuring a double trench structure with a p+-type electric field relaxation region and an n-type high resistance region, which reduces on-resistance and suppresses short channel effects by optimizing impurity concentration and trench geometry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is shortened to reduce on-resistance, then the on-resistance decreases, but the short channel effect and punch-through increase
Solution Approach 1:
The patent introduces a p-type high concentration region specifically at the bottom of the trench gate structure, creating a localized area with different impurity concentration. This local modification allows the channel length to be shortened for lower on-resistance while the high concentration region suppresses punch-through and short channel effects, resolving the contradiction between reducing on-resistance and maintaining reliability.
2Loss of energy
If a trench gate structure is applied to increase channel area, then the on-resistance is reduced, but the device complexity increases
Solution Approach 1:
The patent combines the trench gate structure with a p-type high concentration region at the trench bottom, merging two structural elements into a unified design. This integration achieves both the channel area expansion benefit of the trench gate and the short channel effect suppression of the high concentration region, reducing overall device complexity while maintaining low on-resistance.
3Reliability
If the p-type impurity concentration is increased to suppress punch-through, then the breakdown voltage is maintained, but the manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the p-type impurity concentration parameter in the high concentration region to a specific range (1×10^18 to 1×10^20 atoms/cm³), balancing breakdown voltage maintenance with manufacturability. This parameter optimization reduces the stringency of manufacturing precision requirements while still achieving effective punch-through suppression and reliable breakdown voltage characteristics.
Data Source
AI summary
A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.