SiC MOSFET Trench Gate Structure for Low Turn-On Resistance
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Solution Overview
Problem
Power semiconductor devices, particularly MOSFETs, face challenges in achieving low turn-on resistance and high breakdown voltage, which are essential for reducing power loss and ensuring reliable operation under high current and reverse voltage conditions.
Innovation Solution
A silicon carbide semiconductor device with vertical and horizontal channels is designed, featuring a planar matrix arrangement of trenches, ion doping layers, and a specific gate electrode structure that enhances current density and reduces turn-on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a planar gate MOSFET is used, then the channel is positioned in parallel with the semiconductor surface, but the turn-on resistance increases due to the long current path and presence of JFET region
Solution Approach 1:
The patent transitions from a planar gate structure to a trench gate structure, moving the channel from a parallel arrangement to a vertical arrangement perpendicular to the semiconductor surface. This dimensional change shortens the current path and eliminates the JFET region, simultaneously reducing turn-on resistance while maintaining breakdown voltage characteristics.
Solution Approach 2:
The patent segments the channel into multiple vertical channels formed by trenches extending into the semiconductor substrate. This segmentation creates multiple parallel current paths that reduce the overall turn-on resistance while the trench structure maintains the necessary breakdown voltage through field distribution.
2Loss of energy
If a trench gate MOSFET is used, then the JFET region is eliminated and current path is shortened, but the breakdown voltage decreases due to electric field concentration at the trench bottom
Solution Approach 1:
The patent applies different doping concentrations at different locations within the semiconductor structure. The drift region is doped with a specific concentration to distribute the electric field, while the trench bottom and sidewalls receive additional doping to locally enhance field distribution. This local quality variation prevents electric field concentration at the trench bottom, maintaining breakdown voltage while preserving the low turn-on resistance benefits of the vertical channel structure.
3Area of stationary object
If the semiconductor device area is reduced to improve integration, then the current handling capability may be compromised, but power loss increases if turn-on resistance is not optimized
Solution Approach 1:
The patent utilizes the vertical dimension by creating deep trenches that extend into the semiconductor substrate, forming vertical channels that provide short current paths. This vertical arrangement allows multiple channels to be packed in a compact planar area while maintaining low turn-on resistance, thus reducing power loss without increasing device area.
Solution Approach 2:
The patent optimizes the doping concentration parameters in the drift region and trench structures to achieve low turn-on resistance. By carefully controlling the doping profiles and concentrations, the device achieves minimal power loss in a compact area, as the optimized parameters enable efficient current flow through the vertical channels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves a significant reduction in turn-on resistance and increase in current density, allowing for a smaller semiconductor area while maintaining high breakdown voltage, thus improving power handling efficiency.
Implementation Method 1
The p type region is disposed on a side surface of each of the trenches. The n+ type region is disposed between the side surface of each of the trenches and the p type region, and the ion doping concentration of the n type layer may be higher than the ion doping concentration of the n− type layer.
Data Source
AI summary
A semiconductor device includes an n+ type silicon carbide substrate, an n− type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.