SiC Trench MOSFET Insulation Layout for Sub-4.0 μm Cell Pitch

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Solution Overview

Problem

Conventional vertical MOSFETs with trench structures face challenges in reducing cell pitch due to issues with electric field concentration on the gate insulating film, leading to reliability concerns and increased ON resistance, especially when using wide bandgap semiconductor materials like silicon carbide.

Innovation Solution

The semiconductor device incorporates a structure with a first and second p+-type region, where the first p+-type region is doped with a higher impurity concentration and extends deeper than the trench, and a second p+-type region is provided in a striped shape parallel to the trench, along with a thick interlayer insulating film and a barrier metal, to mitigate electric field concentration and ensure reliable operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a trench structure is formed in a vertical MOSFET to increase cell density, then the current density per unit area increases and cost advantage is achieved, but high electric field concentrates on the gate insulating film at the bottom of the trench, reducing reliability

Engineering Contradiction:
Improvecell density per unit areaVSAvoidgate insulating film reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A p-type base region is introduced as an intermediary structure between the n-type drift layer and the gate insulating film at the trench bottom. This p-type region acts as a mediator that redistributes the electric field, preventing direct concentration on the gate insulating film while maintaining the trench structure's high cell density advantage

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies different doping concentrations and types locally: a p-type base region with high impurity concentration is formed specifically at the trench bottom where electric field concentration occurs, while the surrounding drift layer maintains its n-type characteristics. This local differentiation addresses the reliability issue without compromising the overall device performance

Inventive Principle:
Principle #3Local quality

2Reliability

If a p+-type base region is provided at the bottom of the trench to mitigate electric field concentration, then reliability improves, but the structure complexity increases

Engineering Contradiction:
Improveelectric field distributionVSAvoidtrench structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The p-type base region formation is merged with the existing trench fabrication process sequence. The p-type doping is applied during the same processing steps used to form the trench structure, combining two functions (trench formation and electric field management) into a unified process flow, thereby minimizing additional complexity

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If the cell pitch is reduced below 4.0 μm to increase device integration, then productivity increases, but maintaining effective insulation between gate and source electrodes becomes difficult

Engineering Contradiction:
Improvedevice integration densityVSAvoidinsulation effectiveness
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent transitions from planar insulation approaches to three-dimensional insulation by embedding the gate electrode and interlayer insulating film within the trench structure itself. This vertical dimensionality allows effective insulation between gate and source electrodes even when horizontal pitch is reduced below 4.0 μm, as the insulation is provided through the trench depth rather than lateral spacing

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240405084A1Semiconductor device having gate electrode and interlayer insulating film provided in trench
Publication Date: 2024.12.05 FUJI ELECTRIC CO LTD
  • US20240405084A1 patent drawing
  • US20240405084A1 patent drawing
  • US20240405084A1 patent drawing

AI summary

At a front surface of a silicon carbide base, an n−-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode.