SiC MOSFET U-Shaped Well Self-Aligned Fabrication
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Solution Overview
Problem
Conventional lateral MOSFETs have limited current and power ratings due to narrow channels, while vertical MOSFETs offer higher current capacity but face challenges with channel resistance and device density as feature sizes shrink, especially with silicon carbide materials exhibiting poor mobility and processing issues.
Innovation Solution
A self-aligned method for forming U-shaped wells and source rungs in silicon-carbide MOSFETs, using spacer extensions and area ratio control to reduce channel resistance and increase device density, employing self-alignment techniques to shrink cell dimensions and improve lithography precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If vertical MOSFET configuration is used to increase current capacity, then device power rating is improved, but channel resistance increases due to poor silicon carbide material mobility
Solution Approach 1:
The device is divided into multiple parallel vertical MOSFET cells, each contributing to the total current capacity. By segmenting the device into many smaller cells arranged in parallel, the patent achieves high current capacity while maintaining acceptable channel resistance through the cumulative effect of multiple parallel conduction paths.
Solution Approach 2:
The patent transitions from lateral current flow to vertical current flow, utilizing the third dimension (depth) to create high-density current paths. The vertical channel structure extends from the top surface through the drift region to the bottom surface, enabling compact packaging while maintaining low on-resistance through increased current carrying capacity in the vertical dimension.
2Productivity
If device dimensions are reduced to increase device density, then more devices can be packed in smaller area, but lithographic manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The patent employs preliminary patterning steps where larger features are formed first using standard lithography, followed by self-aligned spacer formation that defines the final small critical dimensions. The spacer width, controlled by thin-film deposition thickness rather than lithography, precisely defines the gate length and other critical dimensions, eliminating the need for high-precision lithography at the smallest feature sizes.
Solution Approach 2:
Spacer structures serve as intermediary elements between the lithographically defined patterns and the final device features. The spacers are formed by depositing conformal thin films over patterned surfaces, and their width is determined by the deposition process rather than lithography, providing a self-aligned method to achieve sub-lithographic feature sizes with high precision.
3Ease of manufacture
If conventional lateral MOSFET structure is used, then manufacturing is simpler, but current capacity and power rating are limited due to narrow channel
Solution Approach 1:
The patent adopts vertical MOSFET structures where current flows vertically from source through channel to drain, utilizing the depth dimension to create high-density current paths. This vertical configuration enables compact device packaging while achieving high current capacity through multiple parallel vertical channels, overcoming the current limits of lateral structures without significantly increasing device footprint.
4Reliability
If source rung area is increased to reduce contact resistance, then reliability improves, but device density decreases due to larger cell area
Solution Approach 1:
The patent optimizes the area ratio of source rungs to body regions as a key parameter to balance contact resistance and device density. By carefully controlling this geometric parameter during device design and fabrication, the patent achieves low contact resistance through adequate source rung area while maintaining high device density through optimized cell layout and compact feature dimensions.
Data Source
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AI summary
In one embodiment, the invention comprises a silicon-carbide MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body region (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and body regions (252). Gate oxide and a gate contact overlie a leg of a well of a first cell and a leg of a well of a second adjacent cell, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.