SiC Planar MOSFET Wave-Shaped Channel Reduces On-Resistance
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Solution Overview
Problem
Conventional silicon carbide (SiC) power MOSFETs face challenges in minimizing specific on-resistance (Ron) while maintaining high blocking voltage, as reducing channel length increases leakage and compromises blocking voltage, and existing approaches require complex processing steps or trade-offs in device performance.
Innovation Solution
A planar SiC MOSFET device structure with serpentine or wave-shaped channel regions is introduced, which reduces lateral transistor cell pitch and increases channel width, thereby lowering Ron without compromising high-voltage blocking capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is reduced to minimize specific on-resistance, then Ron decreases, but leakage increases and blocking voltage is compromised
Solution Approach 1:
The patent applies curvature by transforming the conventional straight channel region into a serpentine or wave-shaped channel region. This curved geometry increases the effective channel width without proportionally increasing the channel length, thereby reducing specific on-resistance while maintaining adequate blocking voltage through the extended lateral path that avoids direct leakage paths.
Solution Approach 2:
The invention transitions from a one-dimensional straight channel to a two-dimensional serpentine pattern. By utilizing the lateral dimension to create multiple winding paths between source and drain, the effective channel width is increased, which reduces channel resistance while the meandering path maintains sufficient electrical length for voltage blocking.
2Loss of energy
If conventional processing steps are used to reduce on-resistance, then Ron decreases, but device complexity increases due to trenches and new technologies
Solution Approach 1:
The patent changes the geometric parameter of the channel region from straight to serpentine/wave-shaped. This parameter modification alone achieves reduced on-resistance without requiring changes in material composition, doping profiles, or additional processing steps such as trenches, thereby maintaining manufacturing simplicity while improving electrical performance.
Data Source
AI summary
A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.