SiC Multi-Trench Layout for Lower On-Resistance
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices with a double trench structure face challenges in reducing on-resistance due to the inability to shrink cell pitch and further reduce resistance, as p-type regions for mitigating electric fields are not disposed at the bottoms of gate trenches, limiting the reduction of on-resistance.
Innovation Solution
A silicon carbide semiconductor device with a multi-trench structure is introduced, where two or more gate trenches are provided for every one source trench, increasing the number of channels and reducing on-resistance by increasing the total area of gate trenches without increasing the number of source trenches, thereby facilitating a narrower cell pitch and enhanced current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a double trench structure with one gate trench per source trench is used, then the device structure is simple and manufacturable, but the on-resistance cannot be reduced further due to limited cell pitch shrinkage
Solution Approach 1:
The gate trench structure is segmented into multiple independent trenches (first gate trenches and second gate trenches) within each unit cell. This segmentation allows each gate trench to function as an independent current channel, increasing the total channel area and reducing on-resistance while maintaining the overall device structure's manufacturability
Solution Approach 2:
The invention transitions from a single gate trench per source trench (1:1 ratio) to multiple gate trenches per source trench (2:1 or higher ratio). This dimensional change in the gate trench configuration increases the total gate trench area and channel density without proportionally increasing the source trench count, thereby reducing on-resistance while controlling cell pitch
2Reliability
If the number of gate trenches is increased to reduce on-resistance, then current density improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Multiple gate trenches (first and second gate trenches) are merged within a single unit cell defined by one source trench. This merging approach increases the effective gate trench density and channel area per unit cell, reducing on-resistance while avoiding the need to proportionally increase source trenches, thus controlling device complexity
Solution Approach 2:
The source trench structure serves multiple functions: it defines the unit cell boundary, provides source contact, and supports multiple gate trenches within its lateral span. This multi-functionality allows the source trench to accommodate increased gate trench density without requiring additional source trenches, reducing on-resistance while maintaining manufacturing simplicity
Data Source
AI summary
A silicon carbide semiconductor device, including: a semiconductor substrate; a first semiconductor region, a second semiconductor region and a plurality of third semiconductor regions provided in the semiconductor substrate; a plurality of first trenches penetrating through the third semiconductor regions and the second semiconductor region in a depth direction and terminating in the first semiconductor region; a plurality of gate electrodes provided in the first trenches via gate insulating films; a plurality of second trenches penetrating through the third semiconductor regions in the depth direction and terminating in the second semiconductor region; and a first electrode and a second electrode provided respectively on two main surfaces of the semiconductor substrate. The second trenches are provided at a predetermined first pitch in a direction parallel to the semiconductor substrate. The first trenches are disposed at a predetermined second pitch in the direction, each between adjacent two of the second trenches.