SiC Multi-Die Package Layout for Low-Inductance High-Frequency Switching
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Solution Overview
Problem
Existing semiconductor device packaging technologies face challenges such as high cost, inferior thermal performance, higher inductance, larger size, and lower level of integration, particularly in high-power applications like power management and automotive systems.
Innovation Solution
The proposed solution involves a package configuration that includes an inner package with multiple silicon carbide dies, each coupled to a common gate conductor, and an outer package with a substrate and a clip that couples to the inner package and substrate, enabling simultaneous switching of multiple semiconductor dies at high frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If leadframe packages and copper clips are used to achieve integration, then device integration is enabled, but cost increases and thermal performance deteriorates
Solution Approach 1:
The patent merges the package substrate and heat sink into a single integrated component, eliminating the need for separate leadframes and copper clips. This consolidation reduces part count and manufacturing complexity while maintaining integration capability, directly addressing the cost increase issue without sacrificing versatility.
Solution Approach 2:
The package substrate is designed to serve multiple functions simultaneously: electrical connection, mechanical support, and thermal management. This multi-functional design replaces the need for separate leadframes (electrical), clips (mechanical), and heat sinks (thermal), reducing overall system cost while maintaining all necessary integration functions.
2Adaptability or versatility
If leadframe packages and copper clips are used to achieve integration, then device integration is enabled, but thermal performance deteriorates
Solution Approach 1:
The package substrate and heat sink are merged into a single component with direct thermal contact to the semiconductor devices. This eliminates thermal interface materials and gaps that exist in traditional leadframe+copper clip configurations, significantly improving heat transfer efficiency while maintaining device integration.
Solution Approach 2:
The package substrate employs composite material structures with high thermal conductivity pathways integrated into the electrical connection layer. This allows simultaneous optimization of both electrical performance and thermal management in a single component, resolving the thermal performance deterioration without compromising integration capability.
3Ease of manufacture
If discrete devices are manufactured separately, then manufacturing cost is reduced, but integration level and size efficiency worsen
Solution Approach 1:
The patent segments the manufacturing process into two stages: simple discrete device fabrication (maintaining low cost) and subsequent mounting onto the integrated package substrate (achieving high integration). This segmentation allows discrete devices to be manufactured using cost-effective processes while the package substrate provides the integration function, resolving both cost and integration level concerns.
4Ease of operation
If traditional packaging approaches are used, then device assembly is simplified, but inductance increases and size increases
Solution Approach 1:
The package substrate integrates electrical connections and grounding paths in a way that minimizes current loop areas, thereby reducing inductance. The direct-mount configuration eliminates long leadframes and external copper clips, creating shorter current paths while maintaining assembly simplicity through the unified substrate structure.
Data Source
AI summary
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.


