Amorphous Silicon Carbide Nitride Memory Dielectric for Data Retention
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Solution Overview
Problem
Charge trapping semiconductor memory cells face challenges in data retention and miniaturization due to limited deep impurities and high leakage current in conventional Si3N4/SiN layers, and previous modifications either fail to generate sufficient deep impurities or reduce storage window size.
Innovation Solution
A multilayer gate dielectric structure incorporating an amorphous silicon carbide and amorphous silicon nitride layer sequence, which increases deep impurity density through network mismatch and dangling bonds, enhancing data retention and charge trapping efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Si3N4/SiN layer is used as the trapping dielectric, then the device structure remains simple, but the deep impurity density is insufficient and leakage current is high
Solution Approach 1:
The patent applies composite materials by combining amorphous silicon carbide and amorphous silicon nitride layers to form a trapping dielectric with superior properties. This composite structure generates sufficient deep impurities through network mismatch while maintaining low leakage current, resolving the contradiction between reliability improvement and device complexity.
Solution Approach 2:
The patent changes the material parameters of the trapping dielectric by using amorphous silicon carbide with specific properties (lower energy band gap, higher electron affinity) combined with amorphous silicon nitride. This parameter change increases deep impurity density and reduces leakage current, improving data retention while managing the increased structural complexity.
2Reliability
If the Si3N4/SiN layer is modified to increase deep impurities, then data retention improves, but the storage window size is reduced
Solution Approach 1:
The patent carefully controls the composition and thickness parameters of the amorphous silicon carbide and amorphous silicon nitride layers. By optimizing these parameters, the invention achieves sufficient deep impurity density for improved data retention while maintaining an adequate storage window size, resolving the contradiction between these two competing requirements.
Solution Approach 2:
The patent applies local quality by creating a layered structure where each material (amorphous silicon carbide and amorphous silicon nitride) performs a specific function. The amorphous silicon carbide generates deep impurities while the amorphous silicon nitride provides additional trapping sites, and their combined local properties achieve both improved data retention and maintained storage window.
3Productivity
If memory cells are miniaturized to increase density, then productivity improves, but data retention deteriorates due to limited deep impurities
Solution Approach 1:
The patent uses composite amorphous silicon carbide/amorphous silicon nitride trapping dielectric that generates sufficient deep impurities even in miniaturized structures. This composite material maintains high deep impurity density despite reduced cell dimensions, enabling both increased memory cell density and preserved data retention.
Solution Approach 2:
The patent changes the material parameters of the trapping dielectric to achieve higher deep impurity density in smaller volumes. The amorphous silicon carbide/amorphous silicon nitride combination provides increased deep impurity generation per unit volume, allowing miniaturization while maintaining data retention performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The amorphous silicon carbide and silicon nitride layer sequence significantly increases deep impurity density, improving data retention and charge trapping efficiency, allowing for further miniaturization of memory cells with reduced leakage currents and increased thermal stability.
Implementation Method 1
The memory layer serves to trap charge carriers, i.e., electrons or holes, between the boundary layers
Implementation Method 2
increases deep impurity density through network mismatch and dangling bonds
Implementation Method 3
a charge trapping semiconductor memory element which can be controlled by means of field effect
Implementation Method 4
allowing for further miniaturization of memory cells with reduced leakage currents and increased thermal stability
Data Source
AI summary
A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.