SiC Package-in-Package Assembly With Common Gate and Silver Sintering

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Solution Overview

Problem

Current power management technologies face challenges with high cost, inferior thermal performance, higher inductance, larger size, and lower integration levels due to the use of leadframe packages and copper clips, which are not suitable for high-performance, high-voltage, and high-frequency applications.

Innovation Solution

A package-in-package configuration using silicon carbide semiconductor die with a common gate conductor and sintered interfaces, where multiple silicon carbide die are coupled to a leadframe and substrate, enabling simultaneous switching and improved thermal performance through a silver sintering process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If leadframe packages and copper clips are used for integration, then device assembly is simplified, but thermal performance deteriorates and inductance increases

Engineering Contradiction:
Improveassembly simplicityVSAvoidthermal performance
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent changes the material parameter from traditional copper clips to silver sintered bonds, which fundamentally alters the thermal and electrical characteristics. Silver sintering provides superior thermal conductivity and lower inductance compared to copper clips, while still maintaining ease of assembly through a standardized bonding process.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention uses silver sintered joints that combine the advantages of both mechanical bonding and metallurgical bonding. The sintered silver creates a composite structure that integrates the leadframe, substrates, and semiconductor devices with optimized thermal and electrical pathways, resolving the contradiction between assembly simplicity and thermal performance.

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If discrete manufacturing is used for high-performance power devices, then manufacturing cost is reduced, but integration level and efficiency deteriorate

Engineering Contradiction:
Improvemanufacturing costVSAvoidintegration level
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent segments the power device into multiple semiconductor dies that can be manufactured using simple discrete processes, then integrates them through a modular package structure. This allows each die to be produced cost-effectively as a discrete component while achieving high integration levels when assembled in the package with multiple dies and substrates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention implements a package-in-package structure where inner packages containing semiconductor dies are nested within an outer package. This nested architecture enables high integration levels by combining multiple discrete devices in a compact arrangement, while each individual die can still be manufactured using cost-effective discrete processes.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If more mask layers are used in IC processes for integration, then integration level increases, but manufacturing cost increases

Engineering Contradiction:
Improveintegration levelVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent divides the integrated circuit function into separate semiconductor dies that require fewer mask layers during fabrication. Each die can be manufactured with simplified processes, and the integration is achieved through the package architecture rather than through complex multi-layer IC fabrication, thereby reducing manufacturing cost while maintaining high integration level.

Inventive Principle:
Principle #1Segmentation

4Volume of moving object

If traditional packaging is used, then device size is reduced, but inductance and thermal performance worsen

Engineering Contradiction:
Improvepackage sizeVSAvoidinductance
Core Design Contradiction:
Volume of moving objectVSObject-generated harmful factors

Solution Approach 1:

The patent changes the electrical parameter of the interconnect structure by using silver sintered bonds instead of traditional copper clips or wire bonds. This parameter change reduces the loop area and inductance of the electrical pathways, achieving low inductance in a compact package size. The silver sintering process creates direct metallurgical bonds that minimize parasitic inductance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces costs, enhances thermal performance, and increases integration levels, allowing for robust operation at high frequencies and voltages while maintaining reliability and yield.

Implementation Method 1

a silver sintering process

Methodology Applied
Scientific EffectSintering: Sintering

Data Source

PatentUS12142551B2Package including multiple semiconductor devices
Publication Date: 2024.11.12 SEMICON COMPONENTS IND LLC
  • US12142551B2 patent drawing
  • US12142551B2 patent drawing
  • US12142551B2 patent drawing

AI summary

In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.