SiC Power Semiconductor Package With Diffusion Soldered Cu Leadframe

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Solution Overview

Problem

Semiconductor packages, particularly those with power semiconductor chips, face challenges in heat dissipation due to high thermal resistance and solder bleed-out issues during attachment to die carriers.

Innovation Solution

A semiconductor package is fabricated using a SiC power semiconductor chip and a Cu leadframe part, where the chip is diffusion soldered to the leadframe, forming at least one intermetallic phase in the solder joint to enhance mechanical and electrical coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If soldering is used to attach the power semiconductor chip to the die carrier, then mechanical coupling is achieved, but solder bleed-out occurs which takes up space and may create short-circuit faults

Engineering Contradiction:
Improvemechanical couplingVSAvoidsolder bleed-out
Core Design Contradiction:
StrengthVSObject-generated harmful factors

Solution Approach 1:

The patent changes the attachment method from conventional soldering to friction stir processing, fundamentally altering the joining parameters and mechanism to eliminate solder bleed-out while maintaining strong mechanical coupling between the power semiconductor chip and die carrier

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the chemical soldering process with a mechanical friction stir processing method, using mechanical energy and material flow control instead of molten solder to achieve the joint, thereby eliminating the harmful solder bleed-out effect

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Temperature

If conventional cooling pathways are used through the die carrier, then cooling is achieved, but thermal resistance remains high reducing cooling efficiency

Engineering Contradiction:
Improvecooling efficiencyVSAvoidthermal resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent optimizes the thermal pathway parameters by creating a direct metallurgical bond between the power semiconductor chip and die carrier through friction stir processing, changing the interface thermal resistance parameters to achieve superior heat dissipation compared to conventional pathways

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent merges the power semiconductor chip and die carrier into a unified thermal pathway through direct bonding, eliminating interface thermal barriers and creating a continuous heat flow path from the chip through the carrier to the heat sink

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces thermal resistance, minimizes solder bleed-out, and ensures reliable electrical and mechanical connections, thereby improving the cooling efficiency and reliability of the semiconductor package.

Implementation Method 1

diffusion soldering the at least one power semiconductor chip to the leadframe part such that the first metal layer and the leadframe part form at least one intermetallic phase

Methodology Applied
Scientific EffectDiffusion soldering: Diffusion Welding

Data Source

PatentUS12205870B2Semiconductor package and method for fabricating a semiconductor package
Publication Date: 2025.01.21 INFINEON TECH AUSTRIA AG
  • US12205870B2 patent drawing
  • US12205870B2 patent drawing
  • US12205870B2 patent drawing

AI summary

A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.