SiC Power MOSFET Pillar Structure for Lower On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current silicon carbide (SiC) power MOSFETs face challenges in reducing on-resistance (Ron) due to low inversion channel mobility, which limits their adoption in lower voltage classes and increases device costs, especially in electric and hybrid electric vehicles, where higher channel mobility is needed to enhance efficiency and reliability.
Innovation Solution
A silicon carbide power device with a unique structure featuring silicon carbide layer stacks, a continuous insulating layer, and a gate electrode layer, where the channel layer is laterally sandwiched between opposing portions of the gate electrode, allowing for a larger conducting area and reduced parasitic capacitance, and the method involves forming pillar-shaped silicon carbide layer stacks without the need for deep trench etching, which simplifies manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar VDMOS design is used, then manufacturing is simpler, but on-resistance is higher due to parasitic JFET effects
Solution Approach 1:
The patent segments the continuous body layer into multiple isolated island regions separated by trenches. This segmentation eliminates the parasitic JFET effect that occurs in planar VDMOS where p-type implantations form continuous gates, thereby reducing on-resistance while maintaining manufacturing feasibility through standard trench formation processes.
Solution Approach 2:
The patent transitions from a two-dimensional planar channel structure to a three-dimensional trench-based structure with islands extending in multiple dimensions. This allows the channel to be formed in regions not laterally interposed between adjacent trench gates, increasing the effective channel area and reducing on-resistance beyond what planar designs achieve.
2Reliability
If trench MOSFET architecture is used, then on-resistance is reduced by eliminating parasitic JFET, but device area is reduced leading to higher on-resistance
Solution Approach 1:
By segmenting the body layer into isolated islands rather than using a continuous body, the patent allows channel formation in regions that would otherwise be occupied by trench structures. This segmentation increases the effective channel area available for conduction while maintaining the benefits of trench architecture in eliminating parasitic JFET effects.
Solution Approach 2:
The patent ensures continuous channel conduction paths through the island regions that are not blocked by adjacent trench gates. This continuity of useful action maintains high current flow capability across the device area, preventing the reduction in effective device area that plagues conventional trench MOSFETs.
3Reliability
If deep trench etching is used for trench MOSFET, then parasitic JFET is eliminated, but manufacturing complexity and cost increase
Solution Approach 1:
The patent uses segmentation of the body layer into islands as a alternative approach to deep trench etching. By forming islands through selective epitaxial growth on patterned sacrificial structures, the patent achieves parasitic JFET elimination without requiring the complex deep trench etching processes needed for conventional trench MOSFETs, thereby reducing manufacturing complexity.
Solution Approach 2:
The patent introduces sacrificial structures as intermediary elements that facilitate island formation. These sacrificial structures are formed through relatively simple patterning processes, and their removal creates the isolated island regions needed to eliminate parasitic JFET effects, serving as a mediator that avoids the complexity of direct deep trench etching.
4Reliability
If inversion channel mobility is low, then device costs increase, but higher mobility requires advanced gate stacks and interfaces
Solution Approach 1:
The patent merges the benefits of trench architecture with island structure to create a hybrid configuration that improves channel mobility through optimized electric field distribution and reduced interface defects. This merging achieves high mobility without requiring the complex advanced gate stacks and interface engineering that would otherwise be needed, thereby reducing device complexity while maintaining high performance.
Data Source
AI summary
A silicon carbide power device having a low on-resistance Ron and a method for manufacturing the same are provided. The silicon carbide power device comprises a first conductivity-type substrate, a plurality of silicon carbide layer stacks, a continuous insulating layer and a gate electrode layer. Each silicon carbide layer stack comprises the following layers stacked on the substrate: a first conductivity-type drain layer, a second conductivity-type channel layer and a first conductivity-type source layer. A plurality of first insulating layer portions laterally cover and surround at least the drain layer and the channel layer of each silicon carbide layer stack. Each point of each channel layer is laterally sandwiched between two opposing portions of the gate electrode layer, wherein the two opposing portions have a distance (d) of less than 2 μm along a straight line extending through that point of that channel layer.