SiC Substrate Pit Etching for Lower On-Resistance
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Solution Overview
Problem
Existing silicon carbide (SiC) power semiconductor devices face limitations in reducing specific on-resistance (RON) and substrate resistance, which hampers their performance and increases manufacturing costs.
Innovation Solution
The method involves forming at least two silicon carbide layers on a substrate, with a pattern of pits created on the opposite side through electrochemical etching, extending completely through the substrate and buffer layer. This process selectively dissolves regions of the SiC substrate, improving device performance by reducing RON and substrate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC substrate structures are used, then manufacturing is simpler, but specific on-resistance and substrate resistance remain high, limiting device performance
Solution Approach 1:
The substrate structure is segmented into multiple functional layers: a first SiC layer (buffer layer) with high doping concentration (≥10^17 cm^-3) to improve interface quality, and a second SiC layer (etch stopper layer) with lower doping concentration to control etching depth. This segmentation allows each layer to perform its specific function optimally, reducing overall resistance while maintaining manufacturability through standardized epitaxial growth processes.
Solution Approach 2:
Different regions of the substrate structure are assigned different doping concentrations tailored to their specific functions. The buffer layer uses high doping (≥10^17 cm^-3) locally at the interface to reduce resistance and improve quality, while the etch stopper layer uses lower doping to provide etching selectivity. This local quality differentiation enables precise control of electrical and etching properties without compromising overall device performance.
2Object-generated harmful factors
If electrochemical etching extends through the substrate and buffer layer, then specific on-resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The etch stopper layer acts as an intermediary between the buffer layer and the underlying substrate. It provides a distinct doping concentration that creates a clear etching boundary, allowing the electrochemical etching process to stop precisely at the desired depth. This intermediary layer mediates the etching process, enabling accurate depth control without requiring extreme manufacturing precision in the etching parameters themselves.
Solution Approach 2:
The doping concentration parameter is changed between layers to create etching selectivity. The etch stopper layer has a lower doping concentration than the buffer layer, which fundamentally changes the etching rate and allows the process to self-limit at the correct depth. This parameter change (doping concentration) provides inherent depth control, reducing the precision burden on the etching process.
3Reliability
If multiple doped epitaxial layers are formed, then on-resistance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The doping concentration parameter is systematically varied across the epitaxial layers to achieve the desired electrical properties. The buffer layer uses high doping (≥10^17 cm^-3) to reduce interface resistance, while the etch stopper layer uses lower doping to provide etching selectivity. These parameter changes are implemented through standard epitaxial growth processes, reducing the need for additional complex manufacturing steps.
Solution Approach 2:
The epitaxial growth process is made multi-functional by varying doping concentrations during the same growth run. A single epitaxial process forms both the buffer layer and the etch stopper layer with different doping levels, eliminating the need for separate fabrication steps. This universality reduces manufacturing complexity while achieving multiple objectives: resistance reduction and etching control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces the specific on-resistance and substrate resistance of SiC power semiconductor devices, leading to improved performance and potentially lower manufacturing costs, without compromising mechanical integrity.
Implementation Method 1
forming a pattern of pits on a second side of the silicon carbide substrate; wherein the pattern of pits, obtained by electrochemical etching, extends completely thorough at least the silicon carbide substrate and the buffer layer
Implementation Method 2
the electrochemical etching process is blocked at the first Nitride-containing layer thanks to the holes barrier height generated at the SiC to Nitride-containing layer heterojunction
Data Source
AI summary
A method forms a part of a power semiconductor device. The method includes homoepitaxially forming two silicon carbide layers on a first side of a silicon carbide substrate and forming a pattern of pits on a second side of the silicon carbide substrate. The two layers include a buffer layer, on the first side of the silicon carbide substrate, and have a same doping type of the silicon carbide substrate and a doping concentration equal to or greater than 1017 cm−3 in order to increase the quality of at least one subsequent SiC layer. The two layers include an etch stopper layer, being deposited on the buffer layer and has a same doping type as the buffer layer but a lower doping concentration in order to block a trenching process. The pattern of pits, obtained by electrochemical etching, extends completely thorough the silicon carbide substrate and the buffer layer.