SiC Planar Gate Structure for Shoot-Through Withstand
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional silicon carbide (SiC) transistor devices face challenges in shoot-through withstand capability due to high gate threshold voltage and Miller capacitance feedback, which can lead to voltage pulses and reduced switching performance.
Innovation Solution
The use of titanium carbide (TiC) source contacts and a planar gate structure with a gate dielectric that overlaps the source and source contact structures, along with a method of manufacturing that forms TiC contacts before gate structure formation, allowing for increased input capacitance and reduced reverse transfer capacitance ratio, thereby mitigating shoot-through issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC transistor devices are used, then high gate threshold voltage provides good off-state control, but Miller capacitance feedback causes voltage pulses and reduces shoot-through withstand capability
Solution Approach 1:
The patent introduces an intermediary structure (gate dielectric overlap region) between the gate and source contact to mitigate the harmful Miller capacitance feedback effect. The gate dielectric extends to overlap the source contact structure, creating a capacitive coupling path that reduces the reverse transfer capacitance and suppresses voltage pulses during switching transitions.
Solution Approach 2:
The patent changes the geometric parameters of the gate structure by extending the gate dielectric beyond the channel region to overlap the source contact. This parameter modification increases the input capacitance while reducing the reverse transfer capacitance, thereby improving the shoot-through withstand capability without sacrificing off-state control.
2Reliability
If gate dielectric is extended to overlap source contact structure, then reverse transfer capacitance is reduced and shoot-through capability is improved, but input capacitance increases
Solution Approach 1:
The patent converts the potentially harmful increase in input capacitance into a beneficial effect. By extending the gate dielectric to overlap the source contact, the increased input capacitance helps suppress voltage spikes and improves shoot-through withstand capability. The design accepts the higher input capacitance as a trade-off to eliminate the more harmful Miller capacitance feedback effect.
3Stability of the object's composition
If titanium carbide contacts are used, then thermal stability is improved and integration flexibility is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the titanium carbide source contacts before depositing the gate dielectric layer. This sequence allows the TiC contacts to be stabilized at high temperatures during the gate dielectric deposition process, ensuring thermal stability and proper integration while simplifying the overall manufacturing process compared to alternative sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the shoot-through withstand capability and switching performance by stabilizing the TiC contacts at high temperatures, allowing for improved thermal budgets and integration sequences, resulting in reduced switching times and increased power handling capability.
Implementation Method 1
stabilizing the TiC contacts at high temperatures, allowing for improved thermal budgets and integration sequences
Data Source
AI summary
A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, a n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.