SiC Power Device Integration With Shielded LV CMOS Regions

The patent merges LV and HV circuit manufacturing onto a single SiC substrate by integrating separate processing sequences into unified steps. Multiple doped regions (first and second conductivity types) are formed simultaneously in different substrate regions, and gate dielectric layers are deposited across both LV and HV regions in the same processing sequence, eliminating the need for separate substrate processing and reducing overall manufacturing time.

The single SiC substrate serves multiple functions by simultaneously supporting both LV CMOS circuits and HV power transistor circuits. The substrate undergoes universal processing steps that accommodate both circuit types, including forming both first and second conductivity type doped regions, depositing gate dielectric layers, and creating various well and drift regions that serve different circuit functions within the same manufacturing framework.

The substrate is segmented into distinct LV regions and HV regions, each with specifically tailored doped regions and structures. LV regions contain first conductivity type well regions and associated circuits, while HV regions contain second conductivity type drift regions and power transistor structures. This spatial segmentation allows complex functions to be distributed across different zones, managing overall process complexity through regional specialization.

Different regions of the substrate are given different local properties through selective doping and structure formation. LV regions receive first conductivity type doping with specific concentration ranges, while HV regions receive second conductivity type doping with different concentration profiles. Gate dielectric layer thicknesses and compositions are also locally optimized for each region's specific electrical performance requirements, allowing complex integrated functionality with region-specific optimization.