SiC Power Module Packaging for Parasitic Inductance Reduction
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Solution Overview
Problem
Current silicon carbide (SiC) power module packaging limitations, such as high parasitic inductance, thermal asymmetry, and increased cost and complexity, hinder the full utilization of SiC devices' benefits in power electronic converters, particularly in applications requiring high power density and reliability.
Innovation Solution
A novel packaging approach featuring an optimized layout design with a side-by-side gate driver connector and low-profile power terminal integrated with a screw thread, combining electric-thermal co-design to reduce parasitic inductance and enhance thermal symmetry, while maintaining a mature fabrication process for cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SiC power module packaging is used, then manufacturing process is mature and cost-effective, but parasitic inductance is high and thermal distribution is asymmetric
Solution Approach 1:
The patent transitions from traditional planar packaging to a 3D stacked architecture where power devices are vertically arranged on a common substrate. This dimensional change enables shorter current paths and reduced parasitic inductance while improving thermal management through vertical heat dissipation paths to heat sinks.
Solution Approach 2:
The patent integrates multiple functions into a unified packaging structure: the common substrate serves as both electrical interconnection and thermal management platform, gate driver connectors are integrated alongside power terminals, and heat sinks are directly coupled to the substrate for combined electrical-thermal optimization.
2Power
If power density is increased, then system efficiency improves, but thermal management becomes more challenging
Solution Approach 1:
The patent employs asymmetric thermal management design where heat sinks are strategically positioned and sized according to the actual heat generation patterns of different power devices. The packaging structure creates symmetric thermal paths from all power devices to the heat sinks, ensuring balanced temperature distribution even with high power density.
3Volume of moving object
If module size is reduced for high power density, then space efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the power module into modular functional units: power device chips mounted on a common substrate, integrated gate driver connectors, and attachable heat sinks. This segmentation allows each component to be manufactured and tested separately using mature processes, then assembled into a compact high-density configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves ultra-low parasitic inductance, threefold increase in power density, balanced current and thermal distribution, and flexible circuit topology, addressing the limitations of traditional SiC power module packaging and enhancing operational reliability.
Implementation Method 1
low-profile power terminal integrated with a screw thread
Implementation Method 2
optimized layout design with a side-by-side gate driver connector and low-profile power terminal integrated with a screw thread, combining electric-thermal co-design to reduce parasitic inductance
Implementation Method 3
combining electric-thermal co-design to reduce parasitic inductance and enhance thermal symmetry
Data Source
AI summary
A rectangular power module with a body having two short ends defining a length and two long sides defining a width having three parallel circuit paths crossing the short width distance from side to side using side positioned gate terminals and planar top positioned top power terminal positioned between MOSFETS in the circuit for even thermal positioning and reduced current path, inductance, and resistance and increased power density.