Vertical Power MOS Transistor on Silicon Carbide
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Solution Overview
Problem
The challenge is to develop a method for manufacturing power MOS transistors on silicon carbide semiconductor substrates that allows for compact devices with low output resistance and high breakdown voltage, while overcoming the limitations of dopant diffusion at high temperatures.
Innovation Solution
The method involves forming body regions and source regions through a series of ion implantations with varying energies, followed by a low-temperature activation process below 1600°C, eliminating the need for thermal diffusion and enabling the creation of deep implanted regions that withstand high breakdown voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature thermal diffusion is used to form doped regions, then dopant activation is achieved, but dopant diffusion causes loss of manufacturing precision and device compactness
Solution Approach 1:
The patent segments the dopant introduction process into two distinct stages: (1) ion implantation to precisely deliver dopants to target depths, and (2) low-temperature plasma treatment to activate dopants without significant diffusion. This segmentation resolves the contradiction by separating the precision positioning function from the activation function.
Solution Approach 2:
The patent changes the temperature parameter from conventional high-temperature thermal diffusion (>1000°C) to low-temperature plasma treatment (<400°C). This parameter change enables dopant activation while preventing the thermal diffusion that compromises manufacturing precision and device compactness.
2Strength
If ion implantation with high energy is used to form deep regions, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple ion implantation steps into a single integrated process that forms both deep and shallow doped regions. By using selective masking and varying implantation conditions within one process flow, the patent achieves high breakdown voltage without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent introduces plasma treatment as an intermediary step between ion implantation and device completion. This plasma intermediary activates the implanted dopants at low temperature, enabling the formation of deep high-voltage regions without requiring complex high-temperature thermal processing sequences.
3Manufacturing precision
If multiple ion implantation steps are used to form precise doped regions, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent combines multiple dopant implantation steps into a single ion implantation process by using different masking patterns and implantation conditions. This merging maintains the precision of multiple steps while reducing the total manufacturing cycle time and improving productivity.
Solution Approach 2:
The patent performs preliminary ion implantation of dopants to precise depths before final device assembly. This preliminary action allows subsequent low-temperature plasma activation without requiring repeated high-temperature processing, thereby maintaining precision while improving overall manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in power MOS transistors with reduced dimensions and low output resistance, capable of withstanding voltages higher than 600V, with the semiconductor substrate thickness remaining identical, and avoids the diffusion issues associated with high-temperature processing.
Implementation Method 1
forming a plurality of deep implanted regions in the semiconductor substrate by ion implantation of a first type of dopant
Implementation Method 2
applying a temperature lower than 1600° C. to the first type of dopant and the second type of dopant to complete formation of the body region, the source region, and the deep implanted region without diffusing of the first and second type of dopants
Data Source
AI summary
A method of manufacturing a vertical power MOS transistor on a wide band gap semiconductor substrate having a wide band gap superficial semiconductor layer, including the steps of forming a screening structure on the superficial semiconductor layer that leaves a plurality of areas of the superficial semiconductor layer exposed, carrying out at least a first ion implantation of a first type of dopant in the superficial semiconductor layer for forming at least one deep implanted region, carrying out at least a second ion implantation of the first type of dopant in the superficial semiconductor layer for forming at least one implanted body region of the MOS transistor aligned with the deep implanted region, carrying out at least one ion implantation of a second type of dopant in the superficial semiconductor layer for forming at least an implanted source region of the MOS transistor inside the at least one implanted body region, and a low budget activation thermal process of the first and second dopant types suitable to complete the formation of the body region, of the source region, and of the deep implanted region with diffusing the dopants in the substrate.