SiC PTC Gate Network for Voltage Overshoot Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
SiC power conversion devices experience increased transconductance with rising junction temperature, leading to faster switching transients and voltage overshoots, which can stress the device and increase switching losses, requiring additional external resistors that add cost and complexity.
Innovation Solution
Incorporating a gate network with a positive temperature coefficient of resistance (PTC) in SiC power conversion devices, allowing the total equivalent series gate resistance to vary with junction temperature, maintaining peak voltages below the maximum rating and reducing switching losses without additional fabrication steps or external resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If external resistors are used to reduce voltage overshoot and dampen oscillations, then voltage overshoot is reduced, but device complexity and cost increase
Solution Approach 1:
The patent merges the gate resistance function with the gate electrode structure itself by forming a doped semiconductor layer directly on the gate. This integration eliminates the need for separate external resistors while maintaining voltage overshoot control, directly resolving the contradiction between reducing harmful voltage overshoot and avoiding increased device complexity
Solution Approach 2:
The gate structure serves dual functions: it provides both the gate control function and the resistance function for dampening oscillations. The doped semiconductor layer inherently provides the necessary resistance without requiring additional components, allowing the device to self-regulate voltage overshoot without external intervention
2Object-affected harmful factors
If external resistors are used to reduce voltage overshoot, then voltage overshoot is reduced, but switching losses increase
Solution Approach 1:
The patent changes the resistance parameter dynamically through temperature-dependent behavior of the doped semiconductor layer. The resistance automatically adjusts based on operating conditions, providing optimal damping at high temperatures when overshoot is most problematic while minimizing resistance at low temperatures to reduce switching losses
3Speed
If gate resistance is reduced to enable fast switching, then switching time decreases, but voltage overshoot increases
Solution Approach 1:
The patent introduces dynamic resistance control through the temperature-dependent properties of the doped semiconductor layer. The resistance is not fixed but adapts to operating conditions, allowing fast switching at low temperatures while automatically increasing resistance at high temperatures to suppress voltage overshoot, thus resolving the static trade-off between switching speed and overshoot control
4Object-affected harmful factors
If external resistors are used to control switching behavior, then voltage overshoot is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the gate electrode formation and resistance element creation into a single fabrication process step. The doped semiconductor layer is formed using standard semiconductor manufacturing techniques during normal gate fabrication, eliminating the need for separate resistor assembly steps and simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PTC gate network ensures peak voltages remain below the maximum rating across varying temperatures, reducing switching losses and oscillations, while maintaining device stability and performance.
Implementation Method 1
a gate network (33) having a positive temperature coefficient of resistance (PTC)
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A gate network of a silicon-carbide (SiC) power conversion device includes a plurality of gate electrodes of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device, and a gate pad disposed in a gate pad and bus area of the SiC power conversion device. The gate network also includes a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device. At least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts- per-million per degree Celsius (ppm/°C).