SiC Rectifier Gate Layout for High-Temperature Annealing
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Solution Overview
Problem
The integration of semiconductor rectifier devices on silicon carbide substrates faces challenges due to high-temperature annealing processes, which damage polysilicon and commonly used gate materials, leading to process integration difficulties and increased costs.
Innovation Solution
A semiconductor rectifier device and manufacturing method that includes forming epitaxial layers, trenches, and doped regions on a silicon carbide substrate, with a gate structure self-alignment process and high-temperature annealing before gate formation, allowing for effective integration without damaging the gate structure and reducing the need for additional photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing process (1700°C or above) is used for activation on silicon carbide substrate, then device performance is improved, but polysilicon and gate materials are damaged
Solution Approach 1:
The patent performs the high-temperature annealing process before forming the polysilicon gate structure. By completing the activation of dopant regions upfront, the subsequent gate formation occurs at lower temperatures that do not damage the polysilicon material, thus resolving the contradiction between achieving device performance and protecting gate materials
Solution Approach 2:
The manufacturing process is divided into distinct stages: first performing high-temperature annealing for dopant activation, then separately forming the gate structure at lower temperatures. This segmentation allows each process to occur under optimal conditions without compromising other components
2Ease of manufacture
If conventional manufacturing process is used, then process integration is simple, but additional photomasks are required and costs increase
Solution Approach 1:
The patent combines multiple process functions into unified steps. The gate structure formation is integrated with the trench isolation process, and dopant activation is combined with the epitaxial growth process. This merging eliminates the need for separate photomask steps while maintaining comprehensive process control
Solution Approach 2:
The epitaxial growth process serves multiple functions simultaneously: it forms the semiconductor layers, activates the dopants through in-situ doping, and creates the required crystal structure. This multi-functionality reduces the total number of process steps and photomasks required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables efficient integration of semiconductor rectifier devices on silicon carbide substrates, reducing damage from high-temperature annealing and lowering overall process costs while maintaining device performance and efficiency.
Implementation Method 1
Semiconductor structures based on silicon carbide substrates require high-temperature (e.g. 1700° C. or above) annealing processes for activation
Implementation Method 2
forming epitaxial layers, trenches, and doped regions on a silicon carbide substrate
Data Source
AI summary
A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.