SiC Rectifier Gate Structure for High-Temperature Annealing
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Solution Overview
Problem
The integration of semiconductor rectifier devices on silicon carbide substrates is hindered by the inability of polysilicon and common gate materials to withstand high-temperature annealing processes, leading to process integration difficulties and increased costs.
Innovation Solution
A semiconductor rectifier device structure and manufacturing method that includes an epitaxial layer, doped regions, a gate structure, and a contact metal layer, with a self-alignment process that allows for high-temperature annealing before gate formation, reducing damage and process costs, and utilizing ion implantation to define doped regions and the gate structure without additional photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing process is used for silicon carbide substrate, then activation of semiconductor structures is improved, but polysilicon and gate materials are damaged
Solution Approach 1:
The process is divided into two distinct stages: first forming the semiconductor structures on silicon carbide substrate, then removing and reconstructing the gate structure. This segmentation allows the high-temperature annealing to be applied without damaging the gate materials, as the gate is removed before the thermal process.
Solution Approach 2:
The gate structure is removed before performing the high-temperature annealing process. This preliminary action prevents the gate materials from being exposed to damaging temperatures, while still allowing the necessary thermal activation of the semiconductor structures to occur.
2Ease of manufacture
If conventional manufacturing process is used for silicon carbide rectifier device, then process integration is achieved, but overall process costs increase
Solution Approach 1:
The gate structure is extracted (removed) from the device temporarily to allow the high-temperature annealing process to proceed without damaging the gate materials. This extraction enables the use of standard silicon carbide processing techniques while avoiding the need for specialized low-temperature processes that would increase costs.
Solution Approach 2:
The processing temperature parameter is changed to high temperatures (suitable for silicon carbide) after the gate structure is removed. This parameter change allows the use of optimized silicon carbide fabrication processes without being constrained by the temperature sensitivity of polysilicon gate materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective integration of semiconductor rectifier devices on silicon carbide substrates, reducing damage from high-temperature processes and lowering overall costs while maintaining device performance and efficiency.
Implementation Method 1
a) performing N-type ion implantation for an area exposed from a first primary surface of silicon chips
Implementation Method 2
rapidly annealing the N-type ions retained in an area bellow the lateral face of the grid electrode to form the upper source/drain area
Data Source
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AI summary
The present application relates to a semiconductor rectifier device and a manufacturing method therefor. The semiconductor rectifier device comprises: an epitaxial layer, which has a top surface and a bottom surface; a first trench, which extends from the top surface to the bottom surface, and comprises a first side wall and a second side wall that are opposite to each other, and a first bottom surface connecting the two side walls; a second trench, which is adjacent to the first trench, and comprises a third side wall and a fourth side wall that are opposite to each other, and a second bottom surface connecting the two side walls; a first doped region, which extends from the top surface to the bottom surface and abuts against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region, which is adjacent to and separated from the first doped region, extends from the top surface to the bottom surface, and abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure, which is disposed on the top surface between the first trench and the second trench, a bottom surface of the gate structure abutting against the first doped region and the second doped region; and a contact metal layer.