SiC Rectifier Gate Self-Alignment After High-Temperature Annealing

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Solution Overview

Problem

The integration of semiconductor rectifier devices on silicon carbide substrates faces challenges due to high-temperature annealing processes, which damage polysilicon and commonly used gate materials, leading to process integration difficulties and increased costs.

Innovation Solution

A manufacturing method for a semiconductor rectifier device that includes forming epitaxial layers, trenches, and doped regions on a silicon carbide substrate, with a gate structure self-alignment process and high-temperature annealing before forming the gate structure, allowing for effective integration and reducing damage from annealing temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-temperature annealing process is used to activate silicon carbide devices, then device performance is improved, but gate materials and polysilicon are damaged

Engineering Contradiction:
Improvedevice performanceVSAvoiddamage to gate materials
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent performs the high-temperature annealing process before forming the gate structure, rather than after. This preliminary action allows the silicon carbide substrate to be activated while avoiding exposure of temperature-sensitive gate materials to high temperatures, thus resolving the contradiction between achieving device performance and protecting gate materials

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The manufacturing process is divided into distinct stages: first performing high-temperature annealing on the silicon carbide substrate, then separately forming the gate structure at lower temperatures. This segmentation allows each process to be optimized independently, with the annealing process achieving full temperature requirements and the gate formation process avoiding thermal damage

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional manufacturing process is used, then process integration is simple, but overall process costs increase due to material damage and rework

Engineering Contradiction:
Improveprocess integrationVSAvoidoverall process costs
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

By performing the high-temperature annealing process before gate formation, the patent eliminates the need for complex protective measures and rework that would be required if gate materials were damaged during or after annealing. This preliminary action simplifies the overall process integration while reducing costs associated with material damage and process rework

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables the successful integration of semiconductor rectifier devices on silicon carbide substrates, reducing process costs and avoiding damage from high-temperature annealing, while maintaining the benefits of silicon carbide's material properties for improved performance.

Implementation Method 1

an epitaxial layer having a top surface and a bottom surface that are opposite to each other

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

a first doped region extending from the top surface to the bottom surface and abutting against the first side wall and at least a part of the first bottom surface of the first trench

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12170340B1Semiconductor rectifier and manufacturing method of the same
Publication Date: 2024.12.17 DIODES INC
  • US12170340B1 patent drawing
  • US12170340B1 patent drawing
  • US12170340B1 patent drawing

AI summary

A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.