SiC Semiconductor Field-Resistant Sealing Material
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Solution Overview
Problem
Existing methods for manufacturing power semiconductor devices using silicon carbide (SiC) face challenges in effectively relaxing electric field intensity at the chip end portions, leading to increased cost and reduced reliability due to insufficient film thickness of highly electric field resistant sealing materials, and prolonged production turnaround time and coating accuracy issues.
Innovation Solution
A semiconductor device and manufacturing method where a highly electric field resistant sealing material is formed with a cross-sectional shape having a perpendicular end face at the chip outer peripheral end and decreasing film thickness towards the inner peripheral end, applied in a wafer state before dicing, allowing for increased film thickness and improved coating accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a highly electric field resistant sealing material is inserted between silicone gel and SiC chip to suppress electric field intensity, then reliability is improved, but film thickness at chip end portion becomes insufficient and cost increases
Solution Approach 1:
The sealing material is designed with spatially varying properties: a first sealing material with high dielectric breakdown field intensity is placed at the chip end portion where electric field intensity is highest, while a second sealing material with lower dielectric breakdown field intensity is placed at the chip center portion. This local differentiation allows each region to be optimized for its specific electric field conditions, ensuring adequate film thickness and reliability at the critical end portion without unnecessary material usage throughout the entire structure.
2Reliability
If termination region is widened to reduce electric field intensity, then reliability is improved, but chip area increases and cost increases
Solution Approach 1:
The invention changes the material parameter (dielectric breakdown field intensity) of the sealing material to withstand higher electric field intensities. By using a sealing material with sufficiently high dielectric breakdown field intensity, the termination region can be designed with smaller area while still maintaining reliability, as the material itself can withstand the concentrated electric field without requiring excessive relaxation space.
3Manufacturing precision
If coating is performed after chip mounting to ensure proper positioning, then coating accuracy is improved, but production turnaround time increases
Solution Approach 1:
The sealing material is coated on the chip before mounting it to the substrate. This preliminary action allows the coating process to be performed on bare chips in a batch manner before assembly, avoiding the need for precise positioning and alignment during coating after mounting. The coating is applied uniformly to all chips before they are mounted, significantly reducing production turnaround time while maintaining adequate coating accuracy.
4Ease of manufacture
If dispenser coating method is used to apply sealing material, then ease of manufacture is improved, but coating accuracy deteriorates due to alignment difficulty
Solution Approach 1:
The sealing material is coated on the chip before mounting, which is the preliminary action that eliminates alignment difficulties. By performing the coating operation before the chip is fixed to the substrate, the dispenser can apply material freely without needing to account for chip position variations, rotation, or height differences that would occur after mounting. This sequence reversal maintains the ease of dispenser coating while dramatically improving coating accuracy and consistency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively relaxes electric field intensity within the sealing material's breakdown limits, enhancing the reliability and cost-efficiency of semiconductor devices by reducing chip area and production time while maintaining high electric field resistance.
Implementation Method 1
Since dielectric breakdown field intensity of SiC is one order of magnitude higher than that of silicon... high dielectric breakdown intensity is required for a sealing material for the SiC
Data Source
AI summary
In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.