SiC Semiconductor Element With Segmented Source Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face reliability issues due to uneven gate oxide layer thickness and the risk of falsely turn-on caused by lowered threshold voltage when attempting to reduce on-resistance, primarily attributed to high-concentration doping and polytype changes during the manufacturing process.
Innovation Solution
A SiC semiconductor element design featuring a semiconductor layer with strategically positioned doped regions and a shallow doped region to control ion implantation depths and angles, ensuring a uniform gate dielectric layer and maintaining a predetermined threshold voltage, thereby reducing turn-on resistance and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-concentration doping is applied to reduce on-resistance, then conduction loss is reduced, but gate oxide layer thickness becomes uneven and reliability deteriorates
Solution Approach 1:
The source region is segmented into multiple doping concentration zones (first source region with lower concentration and second source region with higher concentration), allowing different areas to serve different functions: the lower concentration area ensures uniform gate oxide growth and reliability, while the higher concentration area reduces on-resistance and conduction loss
Solution Approach 2:
Different regions of the source are assigned different doping concentrations based on local requirements: the first source region uses lower concentration for uniform oxide growth, while the second source region uses higher concentration for reduced resistance, optimizing both reliability and conduction loss locally
2Loss of energy
If high-concentration doping is applied to reduce on-resistance, then conduction loss is reduced, but threshold voltage decreases causing falsely turn-on risk
Solution Approach 1:
The source region is divided into first and second source regions with different doping concentrations, where the first source region maintains threshold voltage stability to prevent falsely turn-on, while the second source region reduces on-resistance for lower conduction loss
Solution Approach 2:
Different doping concentrations are applied to different source regions based on functional requirements: the first source region uses lower concentration for threshold voltage stability, while the second source region uses higher concentration for reduced on-resistance
3Ease of manufacture
If ion implantation is performed to form source region, then doping is achieved, but lattice damage occurs and polytype changes happen
Solution Approach 1:
The ion implantation process uses optimized parameters including multiple implantation steps with different doses and energies, followed by controlled annealing processes, to achieve desired doping concentrations while minimizing lattice damage and preventing polytype transformation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces turn-on resistance while maintaining a stable threshold voltage, avoiding the reliability concerns associated with uneven gate oxide thickness and polytype changes, thus enhancing the overall performance and reliability of SiC semiconductor devices.
Implementation Method 1
a first doped region of a second conductivity type opposite the first conductivity type, the first doped region being in the semiconductor layer and including an upper doping boundary spaced from the surface by a first depth D1; a shallow doped region of the second conductivity type, the shallow doped region being in the semiconductor layer and extending from the surface to a shallow doped depth dl
Implementation Method 2
The oxidation rate of SiC depends on the conductivity types, doping concentrations as well as polytypes of SiC. While the gate oxide layer is grown, the high-concentration n-type doped region has a faster oxidation rate than that of a p-type well
Data Source
AI summary
A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.