SiC Semiconductor Short-Circuit Ruggedness via Auxiliary Control

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Solution Overview

Problem

Silicon carbide semiconductor devices face challenges in short-circuit ruggedness, with high short-circuit currents leading to thermal stress and potential irreversible damage during short-circuit conditions.

Innovation Solution

The integration of a normally-on junction field effect transistor (JFET) and an insulated gate field effect transistor (IGFET) in series, along with a unique gate and source region structure, including an auxiliary control structure, to manage voltage drops and thermal stress, ensuring low electrical resistance and high short-circuit ruggedness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a power semiconductor device operates during short-circuit conditions, then the device can detect and respond to short-circuit conditions, but high short-circuit currents cause thermal stress and potential irreversible damage

Engineering Contradiction:
Improveshort-circuit ruggednessVSAvoidthermal stress from short-circuit current
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by designing a saturation current mechanism that preemptively limits the maximum current before thermal damage can occur. The saturation current is engineered to be lower than the damage threshold current, creating a built-in protective effect that activates during short-circuit conditions before irreversible damage can happen to the semiconductor device

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent utilizes parameter changes by dynamically controlling the saturation current through the auxiliary control structure and gate voltage. The saturation current parameter is adjusted based on operating conditions, allowing the device to maintain reliable operation during short-circuit events while preventing thermal stress from reaching damage levels. The saturation current can be modified by changing the gate voltage or auxiliary control signals

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the saturation current is reduced to prevent damage, then short-circuit ruggedness improves, but the voltage drop management becomes more challenging

Engineering Contradiction:
Improveshort-circuit ruggednessVSAvoidvoltage drop
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The patent introduces an intermediary mechanism through the auxiliary control structure that mediates between the saturation current limitation and voltage drop management. The auxiliary control structure acts as an intermediate control element that can independently adjust the saturation current without directly impacting the main current conduction path, thereby preventing voltage drops in the primary circuit while maintaining protective current limiting

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies segmentation by separating the current control function into distinct components: the main current conduction path and the auxiliary control path. This segmentation allows independent optimization of each function - the main path handles power conduction with minimal voltage drop, while the auxiliary path independently manages saturation current limiting for short-circuit protection

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11444155B2Silicon carbide semiconductor device
Publication Date: 2022.09.13 INFINEON TECHNOLOGIES AG
  • US11444155B2 patent drawing
  • US11444155B2 patent drawing
  • US11444155B2 patent drawing

AI summary

A silicon carbide semiconductor device includes a first load electrode disposed on a first surface of a silicon carbide semiconductor body, a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, and an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor including a source region and a body region, the body region being electrically connected to the first load electrode, wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.