SiC Semiconductor Body Region Impurity Gradient for Gate Protection
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Solution Overview
Problem
Silicon carbide semiconductor devices face issues with ruggedness and avalanche breakdown, leading to potential damage to the gate insulating film due to increased voltage differences between the body and gate electrodes.
Innovation Solution
A silicon carbide semiconductor device configuration that includes a silicon carbide layer, a body region, a source region, a gate insulating film, a gate electrode, a source electrode, a first impurity region, and a second impurity region, where the second impurity region connects the body and first impurity regions, with an impurity concentration higher than the silicon carbide layer but lower than the body region, to reduce the electric field applied to the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a P+ type region is provided to reduce voltage difference between outer peripheral structure and body region, then breakdown voltage is improved, but voltage difference between body region and gate electrode increases causing gate insulating film breakdown
Solution Approach 1:
An intermediate impurity region is introduced between the body region and the gate electrode. This intermediate region has an impurity concentration lower than the body region but higher than the drift layer, acting as a voltage gradient mediator that reduces the voltage difference between the body region and gate electrode, preventing gate insulating film breakdown while maintaining high breakdown voltage capability
Solution Approach 2:
The impurity concentration parameter is varied across different regions: the drift layer has low impurity concentration for high breakdown voltage, the body region has high impurity concentration for low on-resistance, and an intermediate impurity region with medium impurity concentration is introduced to create a gradual voltage transition, preventing electric field concentration at the gate electrode interface
2Power
If avalanche breakdown occurs in outer peripheral structure, then high voltage operation is achieved, but voltage increase in body region leads to gate insulating film breakdown
Solution Approach 1:
The intermediate impurity region is pre-configured in the device structure to provide voltage cushioning before avalanche breakdown occurs. When avalanche breakdown happens in the outer peripheral structure, this intermediate region absorbs part of the voltage surge through its specific impurity concentration profile, preventing excessive voltage from reaching the gate electrode and causing breakdown
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ruggedness of the silicon carbide semiconductor device by reducing the voltage difference between the body and gate electrodes, thereby increasing the breakdown voltage and preventing damage to the gate insulating film.
Implementation Method 1
an impurity concentration in the second impurity region is equal to or higher than an impurity concentration in the silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in the body region... to reduce the electric field applied to the gate insulating film
Data Source
AI summary
A silicon carbide semiconductor device includes a silicon carbide layer, a body region, a source region, a gate insulating film, a gate electrode, a source electrode, a first impurity region, and a second impurity region. The second impurity region is disposed within the silicon carbide layer so as to connect the body region and the first impurity region to each other, and has a second conductivity type. An impurity concentration in the second impurity region is equal to or higher than an impurity concentration in the silicon carbide layer and equal to or lower than a lower limit of an impurity concentration in the body region.