SiC Semiconductor Die Bonding with Convex Layer
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Solution Overview
Problem
Existing die bonding methods for semiconductor devices, particularly in high-temperature silicon carbide (SiC) power modules, face challenges in minimizing voids and ensuring reliable heat dissipation due to thin chip thickness and fragile material handling, leading to thermal damage and reduced reliability.
Innovation Solution
A semiconductor device configuration featuring a metallization layer on the backside of the chip, a convex first bonding layer, and a concave second bonding layer between the chip and lead frame, where the convex layer maintains a solid state during bonding while the concave layer melts, effectively eliminating voids by surface tension, ensuring reliable bonding and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a thin Si chip is used for miniaturization, then device efficiency is improved, but heat dissipation properties deteriorate due to reduced heat diffusion capability
Solution Approach 1:
The patent transitions from relying on heat diffusion through the thin chip (one-dimensional path) to heat dissipation through the bonding interface (introducing a new dimensional path). By optimizing the bonding layer structure and interface quality, heat can escape laterally through the lead frame, compensating for the reduced thickness of the chip.
2Device complexity
If conventional die bonding methods are used, then manufacturing simplicity is maintained, but void formation occurs reducing bonding reliability
Solution Approach 1:
The patent changes the physical parameters of the bonding process, specifically controlling the melting point and viscosity of the bonding material, and optimizing bonding temperature and pressure parameters. This allows voids to be eliminated during the bonding process itself without requiring complex additional processing steps.
3Manufacturing precision
If the bonding material is completely melted to ensure bonding, then bonding coverage is improved, but large voids form unavoidably
Solution Approach 1:
The patent applies partial melting of the bonding material rather than complete melting. By controlling the bonding temperature and material properties, only a sufficient portion of the bonding material melts to achieve adequate coverage and bonding, while avoiding the excessive melting that causes large void formation.
4Manufacturing precision
If slits are formed on bonding surface to improve solder flow, then solder distribution is improved, but thermal damage occurs due to unbonded portions
Solution Approach 1:
The patent extracts or removes the problematic slit structure from the bonding surface. Instead of creating unbonded portions through slits, the invention uses a continuous bonding layer that completely covers the bonding surface, eliminating the source of thermal damage while still achieving good solder distribution through other means.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces void formation and enhances the reliability of die bonding, improving heat dissipation properties and minimizing thermal stress, even at high operating temperatures, thus supporting miniaturization and efficiency in power modules.
Implementation Method 1
a first bonding layer that is provided between the semiconductor element and the lead frame, and is bonded to the metallization layer; and a second bonding layer that is provided between the semiconductor element and the lead frame, and bonds the first bonding layer to the lead frame
Data Source
AI summary
The semiconductor device includes; a semiconductor element in which a metallization layer is formed on the backside side; a metallic lead frame that is arranged in parallel, with a distance spaced apart from the semiconductor element; a first bonding layer that is provided between the semiconductor element and the lead frame, and is bonded to the metallization layer; and a second bonding layer that is provided between the semiconductor element and the lead frame, and bonds the first bonding layer to the lead frame. The first bonding layer is expanded at a central portion toward the lead frame.