SiC Semiconductor Device Contact Resistance Optimization
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Solution Overview
Problem
Silicon carbide semiconductor devices, such as JBSs and SBDs, experience significant changes in on-state resistance with temperature variations, leading to unstable current-voltage characteristics, which complicates power circuit design and increases power dissipation.
Innovation Solution
Incorporating a resistance component that decreases with temperature in series with the SiC semiconductor device, and optimizing the contact resistance between the silicon carbide semiconductor and the ohmic junction electrode to maintain a high contact resistance at room temperature, thereby reducing the temperature dependence of on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the contact resistance between the ohmic electrode and semiconductor substrate is reduced to minimize power loss, then power dissipation decreases, but the temperature dependence of on-state resistance increases, leading to unstable current-voltage characteristics
Solution Approach 1:
The patent optimizes the contact resistance parameter to a specific range (0.01Ω≤Rc≤0.1Ω) that balances two competing requirements: low enough to minimize power dissipation (I²Rc losses) but high enough to provide temperature-dependent compensation. This parameter optimization resolves the contradiction by finding the optimal operating point where both low power loss and stable characteristics are achieved simultaneously.
2Strength
If the silicon carbide semiconductor layer thickness is increased to achieve higher breakdown voltage, then breakdown voltage increases, but the on-state resistance increases, leading to higher power dissipation
Solution Approach 1:
The patent optimizes the silicon carbide semiconductor layer thickness parameter (10μm≤d≤50μm) to achieve the desired breakdown voltage while minimizing on-state resistance. By carefully controlling this geometric parameter, the design achieves high breakdown voltage (600V-3000V) without excessive on-state resistance, thus resolving the contradiction between strength and energy loss.
3Loss of energy
If the impurity concentration in the silicon carbide semiconductor layer is increased to reduce on-state resistance, then power dissipation decreases, but the breakdown voltage decreases, reducing device strength
Solution Approach 1:
The patent optimizes the impurity concentration parameter (1×10¹⁶≤Na≤1×10¹⁸ atoms/cm³) to achieve low on-state resistance while maintaining high breakdown voltage. This precise control of electrical parameter allows simultaneous achievement of low power dissipation and high device strength by finding the optimal concentration range where both requirements are satisfied.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the change in on-state resistance due to temperature variations, stabilizes current-voltage characteristics, and decreases power dissipation, enhancing the reliability and efficiency of silicon carbide semiconductor devices.
Implementation Method 1
a second electrode disposed on the second principal surface of the semiconductor substrate and forming an ohmic junction with the semiconductor substrate
Implementation Method 2
a Schottky electrode disposed in contact with the first principal surface and forming a Schottky junction with the first conductivity type semiconductor layer
Data Source
AI summary
A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13≤Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.