SiC Semiconductor Device Field Management for Leakage Suppression
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Solution Overview
Problem
High breakdown voltage semiconductor devices using silicon carbide face challenges in reducing ON resistance, particularly due to high internal electric fields that lead to leakage current and insulating film degradation, making it difficult to achieve low ON resistance while maintaining high breakdown voltage.
Innovation Solution
The semiconductor device design includes specific semiconductor regions and electrode configurations, such as trench-shaped electrodes and strategically positioned contact regions, which reduce the electric field applied to the third semiconductor region, thereby suppressing leakage current and allowing for a low ON resistance even with defects, and maintaining high breakdown voltage by optimizing the position and conductivity of the semiconductor regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high breakdown voltage is achieved in silicon carbide semiconductor devices, then reliability is improved, but internal electric fields increase causing leakage current and insulating film degradation
Solution Approach 1:
The patent applies local quality by creating a third semiconductor region with different conductivity type and characteristics in specific areas where high electric fields occur. This third region is strategically positioned to provide localized field suppression without affecting the overall high breakdown voltage characteristics of the device. The region has different impurity concentration and conductivity compared to surrounding areas, allowing it to specifically address leakage current problems in high-stress zones while maintaining device performance elsewhere.
2Reliability
If high breakdown voltage is achieved in silicon carbide semiconductor devices, then reliability is improved, but insulating film degradation occurs due to high internal electric fields
Solution Approach 1:
The third semiconductor region acts as an intermediary element between the high electric field environment and the insulating film. By positioning this region with different conductivity characteristics adjacent to or overlapping with the insulating film, the patent creates a buffer zone that reduces the electric field stress on the insulating film. This intermediary region absorbs and redistributes the electric field, preventing direct degradation of the insulating film while allowing the device to maintain high breakdown voltage.
3Productivity
If cell pitch is reduced to increase device density, then productivity is improved, but leakage current increases due to higher internal electric fields
Solution Approach 1:
The patent applies local quality by introducing the third semiconductor region with different conductivity characteristics in specific locations within the cell structure. This allows each cell unit to have localized field management capabilities, enabling reduced cell pitch and increased device density without proportionally increasing leakage current. The third region is positioned to address local electric field concentration issues that arise from tighter cell spacing.
Data Source
AI summary
According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.


