SiC Semiconductor Device Vertical Ion Implantation HALO Region

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Solution Overview

Problem

Conventional silicon carbide semiconductor devices with a HALO region face variations in formation positions due to trench dimensions and ion implantation angles, leading to inconsistent unit cell characteristics and increased production complexity, along with longer process times.

Innovation Solution

A silicon carbide semiconductor device structure featuring a p-type base region with differing impurity concentrations, where a high-impurity-concentration region is formed beneath the trench side wall, acting as a HALO to suppress short channel effects and reduce gate threshold voltage, using vertical ion implantation to ensure dimensional accuracy and reduce process complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If oblique ion implantation is used to form a HALO region, then short channel effects are suppressed, but formation position variations occur due to trench dimension and implantation angle differences

Engineering Contradiction:
Improveshort channel effect suppressionVSAvoidHALO region formation position consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Instead of using oblique ion implantation to form the HALO region, the patent inverts the approach by forming the HALO region through vertical ion implantation from the rear surface of the substrate. This reversal of the implantation direction eliminates the position variation problems associated with oblique implantation while maintaining the effectiveness of short channel effect suppression.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from forming the HALO region in the lateral dimension (through oblique implantation from the front surface) to forming it in the vertical dimension (through implantation from the rear surface). This dimensional change allows precise control of the HALO region position relative to the trench structure without being affected by trench dimension variations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If oblique ion implantation is used to form a HALO region, then short channel effects are suppressed, but production complexity and process time increase

Engineering Contradiction:
Improveshort channel effect suppressionVSAvoidproduction efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent simplifies the production process by inverting the implantation approach from oblique front-surface implantation to vertical rear-surface implantation. This inversion eliminates the need for precise angle control and reduces process complexity, thereby improving productivity while maintaining the HALO region's effectiveness in suppressing short channel effects.

Inventive Principle:
Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses short channel effects and reduces gate threshold voltage while maintaining low ON resistance, improving the consistency and efficiency of semiconductor device production by eliminating the need for oblique ion implantation, thus enhancing manufacturing precision and reducing production time.

Implementation Method 1

ion implantation of a p-type impurity to form a p-type high-concentration region

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10930741B2Silicon carbide semiconductor device and method of manufacturing a silicon carbide semiconductor device
Publication Date: 2021.02.23 FUJI ELECTRIC CO LTD
  • US10930741B2 patent drawing
  • US10930741B2 patent drawing
  • US10930741B2 patent drawing

AI summary

A p-type base region is configured by a p−-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.