SiC-Si Parallel Power Device Active Short Circuit Failure Mode
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving compact, secure, and less complex designs for high voltage applications, particularly in series connections where failures can lead to permanent conducting paths, and existing solutions either rely on passive eutectic reactions or complex active bypass mechanisms.
Innovation Solution
A method involving a power semiconductor device with a silicon chip and a wide bandgap material chip, such as SiC, connected in parallel, where the silicon chip is controlled to form a permanent conducting path through eutectic alloy formation with a metal preform upon failure, providing a short circuit failure mode that can be actively triggered by a gate signal, thereby ensuring reliable operation even under overcurrent or thermal breakdown conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive eutectic reaction concepts are used to achieve short circuit failure mode, then reliability is improved, but device complexity increases due to requiring multiple layers and specific material arrangements
Solution Approach 1:
The invention extracts the short circuit failure mode capability from complex mechanical bypass mechanisms and integrates it directly into the semiconductor chip structure through a dedicated short circuit device that can be activated by control signals, eliminating the need for external mechanical bypass components
Solution Approach 2:
The invention replaces passive mechanical eutectic reaction systems with an actively controllable electronic system where a short circuit device can be triggered by gate signals to create a controlled short circuit path, substituting thermal-chemical processes with electrical control mechanisms
2Reliability
If active bypass mechanisms are used to achieve short circuit failure mode, then reliability is improved, but device complexity increases due to requiring additional control circuits and components
Solution Approach 1:
The invention merges the short circuit failure mode functionality directly into the semiconductor chip by integrating a short circuit device with the main power switch, allowing both normal operation and failure mode to be controlled through the same gate signal infrastructure without requiring separate control circuits
Solution Approach 2:
The gate signal that controls normal switch operation also serves to activate the short circuit failure mode when needed, making the control system universal and eliminating the need for dedicated control circuitry for failure mode activation
3Ease of manufacture
If silicon chips are used for high voltage applications, then manufacturing ease is improved, but reliability worsens due to thermal breakdown risks at high temperatures
Solution Approach 1:
The invention prepares a metal preform in advance within the chip structure that will react with the silicon chip upon thermal breakdown to form a low-ohmic resistance path, cushioning the catastrophic effects of thermal breakdown by converting it into a controlled short circuit failure mode that protects the overall system
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact, secure, and less complex power semiconductor devices that can handle high voltages and currents by using the silicon chip's ability to form a low-ohmic resistance path upon failure, ensuring reliable operation and reducing the complexity of mechanical bypass mechanisms.
Implementation Method 1
The eutectic reaction between Si and Al at a relative low temperature (577° C.) may then create a permanent conducting current path as intrinsic failure compensation
Implementation Method 2
the current may heat the Si chip and an Al (aluminium) preform on the chip
Data Source
AI summary
A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.


