SiC-Si Heterostructure MOSFET for Low On-Resistance

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Solution Overview

Problem

Conventional silicon-based power semiconductor devices, such as Si-MOSFETs and SiC-MOSFETs, face limitations in switching speed and energy efficiency due to high channel resistance and breakover voltage, which hinder their performance in high-voltage applications, and wide band gap semiconductors like SiC struggle with low channel mobility and interface defects.

Innovation Solution

A power MOSFET structure is developed with a Si-MOSFET stacked on a SiC drift layer, featuring a trench gate with a bottom position lower than the SiC/Si interface, a barrier layer to moderate electric fields, and a narrow channel effect to reduce on-resistance and enhance voltage endurance, using surface activated bonding technology for wafer integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the thickness of the drift layer is increased to improve voltage endurance in Si-MOSFET, then voltage endurance is improved, but on-state resistance increases leading to higher energy loss

Engineering Contradiction:

Improvevoltage enduranceVSAvoidenergy loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent employs a heterostructure combining SiC drift layer and Si substrate, leveraging the high breakdown field strength of SiC (3x higher than Si) to achieve high voltage endurance while maintaining low on-state resistance. The SiC drift layer thickness can be reduced due to its superior material properties, thereby reducing resistance and energy loss while preserving voltage blocking capability.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The patent changes the material parameter of the drift layer from pure Si to SiC, which fundamentally alters the electric field distribution and breakdown characteristics. This parameter change enables the drift layer to be thinner for the same voltage rating, thus reducing on-resistance and conduction loss while maintaining reliability.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If wide band gap semiconductors like SiC are used to improve voltage endurance and reduce on-resistance, then voltage endurance and speed are improved, but channel mobility decreases due to interface defects

Engineering Contradiction:

Improvevoltage enduranceVSAvoidchannel mobility

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent applies different material qualities to different regions: the drift layer uses SiC for high voltage endurance, while the substrate and channel region use Si for high carrier mobility. The trench gate structure with precise depth control ensures that the channel forms primarily in the high-quality Si region, minimizing the impact of SiC-Si interface defects on channel mobility while still benefiting from SiC's high breakdown field.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The device is segmented into distinct functional regions: SiC drift layer for voltage blocking, Si substrate for high-mobility channel formation, and trench gate for field control. This segmentation allows each region to optimize its material properties for its specific function, achieving both high voltage endurance and high channel mobility.

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If conventional Si-MOSFET structure is used, then manufacturing is easier, but switching loss increases due to slower switching action

Engineering Contradiction:

Improvemanufacturing easeVSAvoidswitching loss

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

The SiC-Si heterostructure enables faster switching by reducing the drift layer thickness while maintaining voltage blocking capability. The thinner drift layer reduces the charge storage and recombination time, thereby reducing switching loss. The manufacturing process builds upon conventional Si-MOSFET techniques while incorporating SiC wafer bonding, achieving a balance between manufacturing ease and improved switching performance.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables low loss and high voltage endurance by improving channel mobility and reducing breakover voltage, allowing for stable current flow and efficient high-voltage operation while minimizing avalanche breakdown and oscillating noise.

Implementation Method 1

a narrow channel effect to reduce on-resistance and enhance voltage endurance

Methodology Applied

Scientific EffectNarrow channel effect:

Implementation Method 2

a barrier layer to moderate electric fields

Methodology Applied

Scientific EffectElectric field modulation: Electric Field

Implementation Method 3

using surface activated bonding technology for wafer integration

Methodology Applied

Scientific EffectSurface activated bonding:

Implementation Method 4

A power MOSFET structure is developed with a Si-MOSFET stacked on a SiC drift layer, featuring a trench gate

Methodology Applied

Scientific EffectField effect transistor operation: Electric Field

Data Source

PatentUS11049942B2Power semiconductor device

Publication Date: 2021.06.29 TSENG TE CHANG

AI summary

A semiconductor device based on SiC-MOSFET realizes high voltage endurance, high current, low breakover voltage, low switching loss and low noise. The SiC-MOSFET is a combination of a Si-MOSFET with high channel mobility and a drift layer formed by SiC with high bulk mobility, so that the first conductive SiC wafer forming the drift layer joins the second conductive Si wafer, excavates out a trench gate in part of the SiC to make the MOSFET, and a second conductive barrier layer is arranged in the Si region adjacent to the SiC.