SiC-Si Superlattice Monolayers for Charge Carrier Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices do not fully leverage advanced materials and processing techniques to achieve optimal performance, particularly in enhancing charge carrier mobility and reducing Schottky barrier height.
Innovation Solution
The development of a superlattice structure with stacked groups of layers, including non-semiconductor monolayers constrained within the crystal lattice of semiconductor portions, which reduces the effective mass of charge carriers and enhances mobility, and incorporates carbon and oxygen as energy band-modifying layers to improve conductivity and act as a barrier against dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor structures are used, then manufacturing simplicity is maintained, but charge carrier mobility is insufficient
Solution Approach 1:
The semiconductor structure is divided into multiple thin monolayer sheets stacked in alternating sequences of different materials (e.g., SiC and Si). Each monolayer is only a few atomic layers thick, creating a segmented superlattice structure that enables enhanced carrier mobility through reduced effective mass while maintaining manufacturability through sequential deposition processes
Solution Approach 2:
The patent employs composite material structures combining different semiconductor materials (SiC/Si superlattice) to achieve properties not possible with single materials. The alternating layers create a composite structure where the interface effects and material properties combine to reduce Schottky barrier height and enhance carrier mobility beyond what either material could achieve alone
2Speed
If higher charge carrier mobility is achieved through material enhancement, then device performance improves, but Schottky barrier height remains insufficiently reduced
Solution Approach 1:
The patent applies local quality enhancement by creating specific regions with different material compositions and properties at the interface between source/drain and channel regions. The SiC/Si superlattice structure provides locally optimized properties at the contact interface, reducing Schottky barrier height specifically where needed for improved carrier injection while maintaining appropriate properties in the channel region
Solution Approach 2:
The patent changes material parameters by introducing alternating monolayers of different bandgap materials (SiC and Si) with varying thicknesses. This parameter modification at the monolayer scale creates quantum mechanical effects and interface states that reduce the Schottky barrier height, enabling better thermal equilibrium and reduced contact resistance without compromising channel performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher charge carrier mobility, reduced source and drain contact resistance, and the ability to provide piezoelectric, pyroelectric, and ferroelectric properties, making the semiconductor devices more efficient and versatile.
Implementation Method 1
incorporates carbon and oxygen as energy band-modifying layers to improve conductivity
Implementation Method 2
which reduces the effective mass of charge carriers and enhances mobility
Implementation Method 3
act as a barrier against dopant diffusion
Data Source
AI summary
A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.


