SiC Chip Sidewall Doping Pattern for Breakdown Voltage Control
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Solution Overview
Problem
Existing semiconductor devices using silicon carbide (SiC) face challenges in optimizing the impurity concentration and crystal orientation for improved electrical characteristics and manufacturing efficiency.
Innovation Solution
The SiC semiconductor device employs a hexagonal SiC monocrystal with specific crystal orientations and controlled impurity concentrations in multiple layers, including a base layer and laminated portions with defined off-angles and channels, to enhance electrical performance and manufacturing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional implantation methods are used to introduce impurities into silicon carbide layers, then manufacturing process is simpler, but impurity concentration distribution and crystal orientation control are insufficient
Solution Approach 1:
The patent applies parameter changes by systematically varying implantation conditions including ion species (boron, aluminum, gallium), implantation energy (10-100 keV), implantation dose (10^14-10^18 ions/cm²), and crystal orientation angles (off-angles from 0-10 degrees) to achieve precise control over impurity concentration distribution and electrical characteristics in silicon carbide layers
Solution Approach 2:
The patent implements local quality by creating distinct impurity concentration profiles in different regions of the silicon carbide structure, including high-concentration implantation regions for contact formation, low-concentration drift regions for voltage blocking, and specifically engineered columnar grain regions with controlled impurity distribution to achieve spatially varying electrical properties
2Reliability
If impurity concentration is increased to improve electrical characteristics, then breakdown voltage increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the impurity distribution into multiple distinct regions with different concentration levels: high-concentration regions (10^18-10^20 atoms/cm³) for ohmic contacts, intermediate-concentration regions (10^16-10^18 atoms/cm³) for junction formation, and low-concentration drift regions (10^14-10^16 atoms/cm³) for voltage blocking, allowing each region to be optimized independently for its specific function
Solution Approach 2:
The patent applies preliminary action by performing multiple sequential implantation steps with progressively adjusted parameters, including pre-implantation of low doses to establish base concentration, followed by higher dose implantation to achieve target concentrations, and final annealing treatments to activate impurities and repair damage before subsequent processing steps
3Manufacturing precision
If channeling implantation is used to improve impurity distribution, then electrical characteristics improve, but process control difficulty increases
Solution Approach 1:
The patent implements feedback control by measuring implantation results through secondary ion mass spectrometry (SIMS) and spreading resistance profiling (SRP) to verify impurity concentration profiles, then using this data to adjust subsequent implantation parameters including dose, energy, and angle to compensate for variations and achieve target concentration distributions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical characteristics and manufacturing efficiency of SiC semiconductor devices by optimizing impurity distribution and crystal alignment, leading to enhanced breakdown voltage and resistance values.
Implementation Method 1
an impurity region introduced into a silicon carbide layer by a channeling implantation method
Data Source
AI summary
The semiconductor device includes a chip having side surface, and an ornamental pattern formed in the side surface. The chip includes a semiconductor layer of a first conductivity type, and the ornamental pattern includes a mark of a second conductivity type that is formed in a portion constituted of the semiconductor layer in the side surface. The side surface includes a first side surface extending in a first direction in plan view and a second side surface extending in a second direction intersecting the first direction in plan view, and the ornamental pattern includes at least one of mark formed in one or both of the first side surface and the second side surface.