High-k Metal Gate CMOS with SiC and SiGe Source/Drain Regions
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Solution Overview
Problem
The conventional high-k metal gate process faces challenges with differing removal rates of sacrificial gate electrode materials in PMOS and NMOS regions, leading to residue issues and increased process complexity and cost due to the hardening of P+ doped PMOS sacrificial gate electrode material during source/drain implantation.
Innovation Solution
Retaining the hard mask on PMOS dummy gate structures during source/drain implantation, which reduces the spacer material layer and equalizes the removal rates of sacrificial gate electrode materials in both regions, simplifying the process flow and improving device performance by forming silicon carbon regions in the NMOS and silicon germanium regions in the PMOS, using epitaxial growth and specific etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If P+ dopant ions are implanted into PMOS sacrificial gate electrode material during source/drain implant, then source/drain regions are formed, but the sacrificial gate material becomes harder to remove causing residue
Solution Approach 1:
The patent applies preliminary action by forming the embedded SiC/SiGe source/drain regions before removing the dummy gate structures. This sequence allows the sacrificial gate material to be removed when it is still relatively soft and easier to etch, avoiding the residue problem that would occur if removal attempted after heavy P+ doping hardened the material.
Solution Approach 2:
The patent segments the source/drain formation process into distinct steps: first forming embedded SiC regions in NMOS and SiGe regions in PMOS, then removing dummy gates, and finally performing ion implantation. This segmentation allows each step to be optimized independently, particularly enabling dummy gate removal at an optimal point before the sacrificial material becomes too hardened.
2Device complexity
If dummy gate structures are removed after source/drain implant, then high-k metal gate structure can be formed, but substantial difference in removal rates between PMOS and NMOS sacrificial gate material occurs
Solution Approach 1:
The patent performs dummy gate removal as a preliminary action before the high-k metal gate structure formation, specifically after embedded SiC/SiGe regions are formed but before ion implantation. This timing ensures uniform removal characteristics and prevents the development of different removal rates that would complicate the subsequent high-k gate formation process.
Solution Approach 2:
The patent changes the physical and chemical parameters of the sacrificial gate material by forming embedded SiC and SiGe regions first, which modify the surrounding environment and stress states. This parameter change ensures that both PMOS and NMOS sacrificial gate materials exhibit similar removal characteristics during the etching process, achieving uniform removal across different device types.
3Ease of manufacture
If hard mask layer is removed from PMOS dummy gate before source/drain implant, then spacer material layer can be reduced, but removal rate difference between PMOS and NMOS sacrificial gate material increases
Solution Approach 1:
The patent maintains the hard mask layer on PMOS dummy gates as a preliminary protective measure during the embedded SiC/SiGe formation process. This preliminary action prevents premature exposure and ensures that both PMOS and NMOS regions develop similar structural characteristics before removal, thereby maintaining uniform removal rates while still allowing spacer reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces process complexity and cost by ensuring consistent removal rates of sacrificial gate electrode materials, enhancing device performance and simplifying the fabrication process by maintaining the hard mask on PMOS regions, thus facilitating the formation of high-k metal gate structures.
Implementation Method 1
forming silicon carbon (SiC) regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the NMOS region, and forming silicon germanium (SiGe) regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the PMOS region
Implementation Method 2
performing ion implant to form source/drain regions in the NMOS region and the PMOS region, respectively
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a PMOS region and an NMOS region in a semiconductor substrate, forming dummy gate structures in the PMOS and NMOS regions, and forming a gate hard mask layer overlying top portions and sidewalls of the dummy gate structures. The method includes forming silicon carbon regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the NMOS region, removing the hard mask layer on top of the dummy gate in the NMOS region, and forming silicon germanium regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the PMOS region. After forming the silicon carbon regions and the silicon germanium regions, while retaining the hard mask layer on top of the dummy gates in the PMOS region, performing ion implant to form source/drain regions in the NMOS region and the PMOS region.