SiC Source/Drain Region for NMOS Electron Mobility
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Solution Overview
Problem
The existing methods for fabricating NMOS transistors face challenges in enhancing electron mobility while maintaining low sheet resistance (Rs), as high temperature thermal processes can lead to carbon atom precipitation and increased sheet resistance due to the formation of SiC in the source/drain regions.
Innovation Solution
A method involving the formation of a silicon substrate with a gate structure, where a SiC region is created with a higher concentration of crystalline SiC beneath the lightly doped drain (LDD) region, using carbon ion implantation and rapid thermal processes to form crystalline SiC without significantly increasing the sheet resistance, by having a first portion of SiC overlapping the source/drain region and a second portion protruding beneath the LDD region with a higher concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high concentration of SiC is formed in the source/drain region to enhance electron mobility, then electron mobility is improved, but sheet resistance increases significantly
Solution Approach 1:
The patent applies local quality by creating a non-uniform SiC concentration distribution within the source/drain region. Specifically, a high SiC concentration is formed in the channel-proximal portion to maximize electron mobility enhancement, while the sheet resistance is controlled by limiting the overall SiC volume and using a gradient concentration profile. This spatial variation in SiC concentration allows different regions to serve different functions: high mobility near the channel and lower resistance in the bulk.
2Quantity of substance
If high temperature thermal processes are used to form SiC, then SiC formation is achieved, but carbon atom precipitation occurs and channel stress is reduced
Solution Approach 1:
The patent employs parameter changes by utilizing rapid thermal processing (RTP) with specifically controlled temperature and time parameters. The RTP process uses high temperature (typically 900-1100°C) for very short durations (seconds to minutes), which enables SiC formation through carbon diffusion and precipitation while minimizing carbon loss from the channel region. This parameter optimization allows SiC formation without excessive thermal exposure that would cause carbon depletion and stress reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electron mobility by maintaining a high SiC concentration near the channel region while keeping the sheet resistance relatively low, effectively addressing the limitations of previous methods.
Implementation Method 1
implanting carbon atoms at a normal angle into the silicon substrate for pre-amorphorizing the silicon of the silicon substrate
Implementation Method 2
performing a rapid thermal process for forming the crystalline SiC
Implementation Method 3
performing a rapid thermal process for forming the crystalline SiC
Implementation Method 4
the embedded silicon carbide (eSiC) in the S/D area is for enhancing NMOS performance due to large tensile stress resulted from the smaller lattice constant of SiC
Data Source
AI summary
A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.