SiC Source Layer Geometry for Low On-Resistance MOSFET Channels
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Solution Overview
Problem
Reducing the channel length in silicon carbide semiconductor devices to lower on-resistance while maintaining a stable threshold voltage is challenging, as it often leads to unstable operations due to the unintended formation of inversion layers.
Innovation Solution
A semiconductor device design featuring a source layer with a side surface shape that approaches the drift layer upward, combined with a manufacturing method involving ion implantation and spacer film control, which allows for independent adjustment of the source layer shape and channel length to maintain a high threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel length is reduced to lower on-resistance, then the on-resistance decreases, but the threshold voltage becomes unstable and operations become unstable
Solution Approach 1:
The source layer is given a specific localized shape where the side surface approaches the drift layer upward, creating a non-uniform structure. This local geometric modification allows the source layer to maintain higher threshold voltage in critical regions while permitting reduced channel length elsewhere, thus resolving the contradiction between low on-resistance and stable threshold voltage
Solution Approach 2:
The source layer shape extends into a third dimension by having its side surface approach the drift layer upward, rather than maintaining a simple planar configuration. This dimensional change creates additional control over the electric field distribution, enabling independent optimization of on-resistance and threshold voltage stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on-resistance while ensuring a stable threshold voltage, suppressing the formation of inversion layers and maintaining device stability even at reduced channel lengths.
Implementation Method 1
forming a second semiconductor layer in a portion of an upper portion of the first semiconductor layer by implanting a first impurity into the first semiconductor layer by using the mask member as a mask
Implementation Method 2
forming a spacer film on the first semiconductor layer and on the second semiconductor layer. The spacer film covers the mask member
Implementation Method 3
forming a third semiconductor layer in a portion of an upper portion of the second semiconductor layer by implanting a second impurity into the second semiconductor layer via the spacer film by using the mask member as a mask
Data Source
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AI summary
A semiconductor device includes a first electrode, a first semiconductor layer connected to the first electrode, a second semiconductor layer located on a portion of the first semiconductor layer, a third semiconductor layer located on a portion of the second semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode located in a region directly above at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer faces the first semiconductor layer via the second semiconductor layer. A side surface of the third semiconductor layer facing the first semiconductor layer has a shape that approaches the first semiconductor layer upward. The third semiconductor layer is of a first conductivity type and includes silicon and carbon. The third electrode faces the portion via a first insulating film.