Silicon carbide semiconductor device
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices face challenges in reducing JFET resistance while maintaining effective electric field mitigation near the bottoms of gate trenches, often requiring proximity of gate and source trenches which increases JFET resistance when p-type deep base portions are not disposed at the bottoms of source trenches.
Innovation Solution
A silicon carbide semiconductor device with a trench gate structure featuring source trenches and gate trenches, where the source trenches are deeper than gate trenches, and p-type deep base portions are formed at the bottoms of the source trenches to mitigate electric fields at the gate trenches without additional p-type regions, reducing JFET resistance by increasing the width of the JFET portion and allowing for deeper p-type deep base portions to enhance short-circuit capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source trenches and gate trenches are disposed in proximity to mitigate electric field at gate trench bottoms, then electric field mitigation is improved, but JFET resistance increases
Solution Approach 1:
The patent applies local quality by forming p-type deep base portions specifically at the bottoms of source trenches, creating a localized doped region with different electrical properties. This localized modification allows electric field mitigation at the gate trench bottoms without requiring proximity of source and gate trenches, thereby avoiding increased JFET resistance while maintaining reliability
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement where source and gate trenches must be close for electric field mitigation to a three-dimensional solution where p-type deep base portions extend vertically from source trench bottoms. This vertical extension into the depth dimension provides electric field mitigation without compromising the horizontal spacing needed for low JFET resistance
2Reliability
If p-type deep base portions are formed at bottoms of source trenches, then electric field mitigation is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of p-type deep base portions with the existing source trench structure. The p-type doping is integrated into the source trench region during manufacturing, combining multiple functions (source contact, electric field mitigation, and JFET resistance control) into a single structural element rather than adding separate components
Solution Approach 2:
The p-type deep base portions serve multiple functions simultaneously: they provide electric field mitigation at gate trench bottoms, maintain low JFET resistance through appropriate spacing, and can be formed using standard semiconductor doping processes. This multi-functionality reduces the need for additional specialized structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces JFET and on-resistance, enhances reliability by effectively mitigating electric fields at the gate trenches, and supports higher voltage classes like 1200V or greater without adverse effects on gate characteristics.
Implementation Method 1
Portions (hereinafter, p-type deep base portions) 104 of the p-type base region 103 along bottoms of the source trenches 111 form pn junctions with the n-type drift region 102
Data Source
AI summary
A silicon carbide semiconductor device, including: a semiconductor substrate; a first semiconductor region, a second semiconductor region and a third semiconductor region provided in the semiconductor substrate; a first trench penetrating through the third semiconductor region and the second semiconductor region in a depth direction and terminating in the first semiconductor region; a gate electrode provided in the first trench, via a gate insulating film; a plurality of second trenches penetrating through the third semiconductor region in the depth direction and terminating in the second semiconductor region; a fourth semiconductor region provided opposing, in the depth direction, a portion of the second semiconductor region that is below a bottom of each of the plurality of second trenches; and a first electrode and a second electrode provided at two main surfaces of the semiconductor substrate.