SiC Power Semiconductor Spacer Alignment for Reduced Cell Pitch
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Solution Overview
Problem
The challenge in manufacturing SiC power semiconductor devices is the difficulty in achieving cost-effective production while maintaining performance characteristics, particularly due to limitations in wafer processing equipment and trade-offs with breakdown voltage and cell pitch dimensions.
Innovation Solution
The use of spacer structures to form features such as recesses and doped regions self-aligned to opposing sides of the spacer, allowing for reduced cell pitch without the need for expensive photolithographic processing equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic processing equipment is used to achieve reduced cell pitch, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent uses spacer structures as intermediary elements to define the cell pitch dimensions. Instead of directly using photolithography to define the pitch, spacers are formed as intermediate structures that self-align to mask features, thereby transferring the dimensional control to a simpler process step that does not require expensive photolithographic equipment.
Solution Approach 2:
The patent replaces the optical measurement and patterning system (photolithography) with a mechanical/chemical deposition and etching system. The cell pitch is defined by the thickness of deposited spacer material and subsequent anisotropic etching, which are simpler and more cost-effective processes compared to high-precision photolithographic equipment.
2Productivity
If cell pitch is reduced to improve on-resistance, then productivity is improved, but manufacturing precision requirements increase beyond typical equipment tolerances
Solution Approach 1:
The spacer structures self-align to the mask features through conformal deposition, automatically defining the cell pitch without requiring external alignment systems. This self-aligning mechanism inherently compensates for variations in mask dimensions and deposition uniformity, achieving precision beyond what would be possible with direct photolithographic patterning.
Solution Approach 2:
The mask features are formed first with relaxed tolerance requirements, and then the spacer structures are deposited to define the final cell pitch dimensions. This preliminary formation of mask features with less stringent requirements allows the subsequent spacer-based process to achieve the required precision without demanding ultra-precise mask fabrication.
3Manufacturing precision
If advanced processing techniques are used to reduce cell pitch, then on-resistance is improved, but ease of manufacture deteriorates due to cost prohibitive equipment
Solution Approach 1:
The patent uses disposable mask structures that are formed with simple, low-cost processes. These masks are not required to maintain their dimensions throughout the entire process like photomasks, allowing the use of cheaper, less precise mask fabrication methods. The masks serve their purpose of defining the spacer alignment and are then removed, eliminating the need for expensive, reusable photolithographic equipment.
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a body of semiconductor material including a substrate and a semiconductor region over the substrate. The method includes providing a spacer over the semiconductor region. The method includes providing a first feature as part of the body of semiconductor material self-aligned to a first side wall of the spacer and providing a second feature as part of the body of semiconductor material self-aligned to a second side wall of the pacer. A portion of the semiconductor region is laterally interposed between the first feature and the second feature, the first feature and the second feature can be doped regions or recesses, and the portion of the semiconductor region laterally interposed between the first feature and the second feature comprises a channel region of a JFET semiconductor device or a JFET region of an insulated gate field effect transistor device.