SiC Split-Gate Source Contact Layout to Eliminate Overlay Errors
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Solution Overview
Problem
Conventional semiconductor devices face challenges in high-density integration due to contact-to-trench overlay errors during source contact formation, leading to increased fabrication costs, manufacturing cycle time, and device reliability issues such as UIS failure and component burnout.
Innovation Solution
A semiconductor device with a split gate structure and self-aligned contact features is developed, utilizing a silicon carbide substrate, epitaxial layer, and shielding dielectric layers to form self-aligned source contacts, reducing the need for high-resolution masks and minimizing overlay errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional source contact formation processes are used, then manufacturing process is simpler, but overlay errors increase leading to reduced manufacturing precision
Solution Approach 1:
The gate structure is segmented into two separate gate electrodes (first gate electrode and second gate electrode) positioned on opposite sidewalls of the first electrode. This segmentation enables self-alignment of the source contact with the trench, eliminating overlay errors while maintaining manufacturing feasibility through standardized fabrication processes
Solution Approach 2:
The first electrode serves as an intermediary structure between the source contact and the trench. By positioning the split gate structure on opposite sidewalls of this intermediary electrode, the design achieves self-alignment without requiring high-precision overlay, thus resolving the contradiction between manufacturing precision and device complexity
2Manufacturing precision
If high-resolution masks are used to reduce overlay errors, then manufacturing precision improves, but fabrication cost increases
Solution Approach 1:
The split gate structure on opposite sidewalls of the first electrode creates a self-aligning feature that automatically positions the source contact correctly without requiring high-resolution photomasks or complex alignment procedures. This self-service mechanism eliminates the need for expensive advanced lithography equipment and reduces fabrication costs while maintaining high overlay precision
3Reliability
If conventional contact formation is used, then device structure is simpler, but reliability decreases due to overlay errors
Solution Approach 1:
Dividing the gate into two separate electrodes on opposite sidewalls creates a self-aligned configuration that eliminates overlay errors, directly improving device reliability. The segmentation approach ensures consistent electrical characteristics and prevents UIS failure and component burnout associated with misalignment, while the structure remains manageable through standard fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing efficiency, reduces fabrication costs, and improves device reliability by minimizing overlay errors and electrical parameter variations, thereby improving switching characteristics and reducing on-resistance.
Implementation Method 1
growing an epitaxial layer on a top surface of the silicon carbide substrate
Data Source
AI summary
A semiconductor device and a method for forming the same are provided. The semiconductor device includes a silicon carbide substrate, an epitaxial layer, a first electrode, a split-gate structure and a source contact. The epitaxial layer is disposed on a top surface of the silicon carbide substrate. The silicon carbide substrate and the epitaxial layer have a first conductivity type. The first electrode is disposed in the epitaxial layer in the first region and extends along a first direction. The split-gate structure includes a first gate electrode and a second gate electrode located on opposite side walls of the first electrode. A top portion of the first electrode is exposed from the split-gate structure. The source contact is disposed on the epitaxial layer in the first region. The source contact covers and is electrically connected to the top of the first electrode.