SiC Semiconductor Device Stacking Fault Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices with silicon carbide (SiC) materials face deterioration in characteristics due to the occurrence and expansion of stacking faults caused by current stress, leading to increased forward voltage and reduced performance.
Innovation Solution
The semiconductor device is designed with a configuration that adjusts the total value of the change amount of chemical potential and stacking fault energy to be zero or more, suppressing the occurrence and expansion of stacking faults by optimizing impurity concentration and thickness of layers, and optionally incorporating trenches in the support substrate to control the expansion direction of stacking faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC-based power semiconductor devices are used, then better characteristics than Si-based devices are achieved, but crystal defects change into stacking faults due to current stress causing characteristics deterioration
Solution Approach 1:
The patent applies preliminary anti-action by introducing a specific layer structure with controlled impurity concentrations and thicknesses before the stacking faults can occur. The semiconductor device includes a first semiconductor layer and a second semiconductor layer with specific impurity concentration relationships that preemptively counteract the formation and expansion of stacking faults under current stress, preventing the harmful effect before it manifests.
Solution Approach 2:
The patent utilizes parameter changes by precisely controlling the impurity concentrations and thicknesses of different semiconductor layers. The first semiconductor layer has a first impurity concentration and the second semiconductor layer has a second impurity concentration with specific relationships between them. By adjusting these parameters (impurity concentrations, layer thicknesses), the device optimizes its resistance to stacking fault formation while maintaining electrical performance.
2Reliability
If stacking faults occur and expand due to current stress, then forward voltage increases and performance reduces, but device structure becomes more complex to prevent this
Solution Approach 1:
The patent applies local quality by creating regions with different impurity concentrations at specific locations within the semiconductor device. The first semiconductor layer and second semiconductor layer have different impurity concentrations tailored to their specific functional requirements. This localized differentiation allows the device to maintain overall simplicity while providing targeted protection against stacking faults in critical regions.
Solution Approach 2:
The patent employs composite materials by combining semiconductor layers with different impurity concentrations and compositions. The first semiconductor layer and second semiconductor layer form a composite structure where each layer contributes different properties - one layer provides electrical functionality while the other provides stacking fault resistance. This composite approach achieves enhanced reliability without requiring fundamentally new materials, maintaining manufacturing feasibility.
Data Source
AI summary
According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.