SiC Stacking Fault Memory via Stress-Induced Resistance Variation
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Solution Overview
Problem
Conventional semiconductor storage devices based on silicon (Si) materials have limitations in performance due to lower breakdown electric fields, thermal conductivity, and electron mobility, whereas hexagonal crystalline compound semiconductors offer higher performance but face challenges in utilizing stacking faults for data storage effectively.
Innovation Solution
A semiconductor storage device utilizing a hexagonal crystal structure SiC material with basal plane dislocations, where electrical and thermal stresses are applied to expand and contract stacking faults to vary resistance values, enabling nonvolatile and rewritable data storage by associating bit values with the state of these faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hexagonal crystalline compound semiconductors are used to improve device performance through higher breakdown electric field, thermal conductivity, and electron mobility, then device performance increases, but the complexity of utilizing stacking faults for data storage increases
Solution Approach 1:
The patent changes the physical state and electrical parameters of the semiconductor material by introducing controlled stacking faults in hexagonal crystalline compound semiconductors. By varying the stacking sequence (e.g., ABCABC for perfect crystals vs. ABCACB for faults), the electrical resistance changes dramatically, enabling data storage functionality while maintaining the inherent high-performance properties of the hexagonal crystal structure
Solution Approach 2:
The patent creates a composite structure within the semiconductor by combining regions with different stacking fault characteristics. This includes integrating basal plane dislocations with stacking fault zones to form a composite material system that simultaneously achieves high breakdown electric field, good thermal conductivity, and controllable resistance states for memory functionality
2Adaptability or versatility
If stacking faults are introduced to enable data storage functionality, then nonvolatile and rewritable storage capability is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary actions during the semiconductor fabrication process to intentionally create stacking faults before final device assembly. This includes using controlled ion implantation, selective epitaxial growth interruptions, or mechanical stress applied during manufacturing to pre-form the desired stacking fault patterns that will provide the memory functionality in the finished device
Solution Approach 2:
The patent introduces intermediary processes and materials to facilitate precise stacking fault creation. This may include using intermediary layers during epitaxial growth, employing intermediary stressors during fabrication, or utilizing intermediary ion implantation techniques that allow indirect but controlled formation of stacking faults with high precision
3Ease of operation
If electrical and thermal stresses are applied to expand and contract stacking faults for variable resistance, then rewritable storage is enabled, but energy consumption increases
Solution Approach 1:
The patent employs periodic application of electrical and thermal stresses to rewrite data in the stacking fault memory. By applying stress pulses at specific intervals and durations, the stacking faults can be repeatedly expanded and contracted to change resistance states, enabling rewritable storage while optimizing energy consumption through controlled pulse timing and duration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a high-performance semiconductor storage device that can store information using the characteristics of stacking faults, providing a nonvolatile and rewritable, variable resistance storage capability, enhancing device performance and capacity.
Implementation Method 1
electrical and thermal stresses are applied to expand and contract stacking faults to vary resistance values
Implementation Method 2
electrical and thermal stresses are applied to expand and contract stacking faults to vary resistance values
Data Source
AI summary
A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.