SiC Epitaxial Wafer Step Bunching for Polytype Contamination
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Solution Overview
Problem
Silicon carbide (SiC) epitaxial wafers with low off-angles struggle with contamination by different polytypes and impurity nitrogen capture, especially at high C/Si ratios, which hinders the production of reliable high-voltage semiconductor elements.
Innovation Solution
Creating step bunching on the silicon carbide substrate through hydrogen etching and forming an epitaxial layer at a high C/Si ratio, followed by chemical mechanical polishing to reduce contamination and achieve a smooth surface, with a region of 90% or more bunched steps of 1 nm in height along the substrate's cross-section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a low off-angle substrate (less than 4°) is used to reduce production cost and control anisotropicity, then manufacturing cost is reduced and anisotropicity is controlled, but contamination by different polytypes increases and impurity nitrogen capture increases
Solution Approach 1:
The patent applies preliminary action by forming step bunching on the substrate surface before epitaxial growth. This pre-treatment modifies the substrate surface morphology to create a structure that prevents polytype contamination during subsequent growth, allowing low off-angle substrates to be used without suffering from contamination issues.
Solution Approach 2:
The patent changes the surface morphology parameter by creating step bunching with specific characteristics (5-10 bunched steps of 1 nm height occupying 90% or more of the surface). This parameter change in surface structure fundamentally alters the growth behavior, enabling contamination-free epitaxial growth on low off-angle substrates.
2Reliability
If a low C/Si ratio is used to reduce polytype contamination, then contamination by different polytypes is reduced, but carrier-trapping centers increase and impurity nitrogen capture increases
Solution Approach 1:
The step bunching formation before epitaxial growth serves as a preliminary action that fundamentally changes the growth mechanism. This allows the use of high C/Si ratios without generating polytype contamination, thereby eliminating the need to use low C/Si ratios that would otherwise be required to prevent contamination.
Solution Approach 2:
The patent converts the potentially harmful high C/Si ratio conditions into a beneficial outcome. By pre-forming step bunching, the high C/Si ratio growth that would normally cause contamination instead produces high-quality epitaxial layers with fewer carrier-trapping centers and less impurity nitrogen capture.
3Reliability
If a 4° off-angle substrate is used to reduce polytype contamination, then contamination by different polytypes is reduced, but manufacturing cost increases and anisotropicity control is reduced
Solution Approach 1:
By performing step bunching formation as a preliminary treatment on low off-angle substrates, the patent enables these substrates to achieve the same contamination resistance as traditional 4° substrates, while maintaining the cost and anisotropicity control advantages of low off-angle materials.
Solution Approach 2:
The patent changes the surface morphology parameter (creating step bunching) to compensate for the low off-angle of the substrate. This parameter change in surface structure allows low off-angle substrates to achieve contamination levels comparable to or better than traditional 4° substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contamination by different polytypes and impurity nitrogen capture, enabling the production of reliable high-voltage silicon carbide semiconductor elements by ensuring a high proportion of step bunching on the substrate surface.
Implementation Method 1
Creating step bunching on the silicon carbide substrate through hydrogen etching
Implementation Method 2
forming an epitaxial layer at a high C/Si ratio
Implementation Method 3
forming an epitaxial layer at a high C/Si ratio
Implementation Method 4
chemical mechanical polishing to reduce contamination and achieve a smooth surface
Data Source
AI summary
A subject of present invention is to enable reducing, even in growth at a high C/Si ratio, contamination by different polytypes with respect to a silicon carbide epitaxial wafer having a low off-angle, and to provide the silicon carbide epitaxial wafer which enables forming a reliable high voltage silicon carbide semiconductor element.The silicon carbide epitaxial wafer of the present invention is a silicon carbide epitaxial wafer comprising an epitaxially grown layer disposed on a silicon carbide substrate having an α-type crystal structure and an off-angle tilted at an angle of more than 0° and less than 4° from a (0001) Si plane or a (000-1) C plane, wherein a region of a step bunching including five to ten bunched steps of 1 nm in height occupies 90% or more of the surface of the silicon carbide substrate.