SiC Substrate Emission Ratio to Suppress BPD Stacking Faults
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Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face challenges with basal plane dislocations (BPD) expanding into stacking faults (SF), leading to increased ON voltage due to the influence of planar defects, which existing technologies have not effectively addressed.
Innovation Solution
A SiC substrate is designed with an emission peak at 650 to 750 nm that is 4.5 times or more of the emission peak at 385 to 408 nm, and an epitaxial layer with specific impurity concentrations and thicknesses, suppressing the expansion of BPD into SF by controlling carrier lifetime through defect management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC substrates are used, then manufacturing is easier, but BPD expands into SF leading to increased ON voltage and reduced reliability
Solution Approach 1:
The patent applies parameter changes by controlling the emission peak ratio (650-750 nm / 385-408 nm) to be 4.5 or more, which corresponds to changing the carrier lifetime parameter to 2.5 ns or less. This parameter control prevents BPD expansion into SF while maintaining manufacturing feasibility through established SiC substrate production methods.
2Duration of action of moving object
If carrier lifetime is extended, then device performance improves, but BPD expansion into SF is promoted increasing ON voltage
Solution Approach 1:
The patent converts the potentially harmful effect of carrier lifetime (which can promote BPD expansion) into a beneficial parameter by establishing the emission peak ratio threshold of 4.5 or more. This corresponds to carrier lifetime of 2.5 ns or less, which actually suppresses BPD expansion into SF while maintaining adequate device performance through proper epitaxial layer design.
3Productivity
If epitaxial layer thickness is increased, then device performance improves, but defect influence increases leading to higher ON voltage
Solution Approach 1:
The patent applies local quality by creating a buffer layer with specific impurity concentration (1.0×10^18 to 1.0×10^19 cm^-3) and thickness (3 to 10 μm) between the substrate and the drift layer. This localized structural design with controlled properties suppresses BPD expansion into SF in the critical region while allowing the drift layer to maintain adequate thickness for device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively restricts the expansion of BPD into SF, improving the reliability and performance of SiC semiconductor devices by maintaining a shorter carrier lifetime and desired characteristics, such as specific resistance and impurity concentrations.
Implementation Method 1
an emission peak of the substrate at a wavelength of 650 to 750 nm is set to be 4.5 times or more of an emission peak of the substrate at a wavelength of 385 to 408 nm in an electronic excitation
Data Source
AI summary
A silicon carbide substrate includes a substrate made of silicon carbide. An emission peak of the substrate at a wavelength of 650 to 750 nm is 4.5 times or more of an emission peak of the substrate at a wavelength of 385 to 408 nm in an electronic excitation. An integral value related to an emission peak of the substrate at a wavelength of 650 to 750 nm is 15 times or more of an integral value related to an emission peak of the substrate at a wavelength of 385 to 408 nm in an electronic excitation.