SiC Substrate Manufacturing via Selective Front Surface Polishing
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Solution Overview
Problem
The manufacturing of silicon carbide (SiC) substrates for power devices is hindered by the need for extensive polishing, which increases lead time and cost due to differences in surface roughness between the front and back surfaces, making it challenging to achieve optimal epitaxial growth and device performance.
Innovation Solution
A manufacturing method that involves grinding both the front and back surfaces of sliced SiC substrates to an arithmetic mean height of 1 nm or less on the back surface, followed by polishing only the front surface, to reduce warpage and streamline the production process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polishing is applied to both front and back surfaces of sliced SiC substrate, then warpage is reduced and substrate flatness is improved, but manufacturing lead time increases and manufacturing cost increases
Solution Approach 1:
The patent applies different surface treatment processes to different surfaces of the SiC substrate. The front surface (Si-face) undergoes both grinding and polishing to achieve high flatness for epitaxial growth, while the back surface (C-face) undergoes only grinding to achieve Sa≤1nm. This local differentiation maintains substrate flatness while reducing manufacturing lead time and cost by eliminating unnecessary polishing on the back surface.
Solution Approach 2:
Instead of applying full polishing treatment to both surfaces, the patent applies partial action by performing polishing only on the front surface where it is critical for device performance. The back surface receives sufficient grinding treatment (Sa≤1nm) to control warpage without the time-consuming polishing step, achieving acceptable flatness control with reduced manufacturing cycle.
2Manufacturing precision
If polishing is applied to both front and back surfaces of sliced SiC substrate, then substrate flatness is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements local quality by applying polishing only to the front surface (Si-face) where high flatness is critical for epitaxial growth and device performance. The back surface (C-face) is treated with grinding alone to achieve Sa≤1nm, which is sufficient for warpage control. This selective approach reduces manufacturing cost by eliminating unnecessary polishing operations on the back surface while maintaining required substrate quality.
3Loss of time
If only front surface is polished without back surface polishing, then manufacturing lead time is shortened and cost is reduced, but warpage control may be insufficient
Solution Approach 1:
The patent applies preliminary action by performing thorough grinding treatment on the back surface (C-face) before polishing the front surface. The grinding process achieves Sa≤1nm on the back surface, which pre-controls the substrate flatness and minimizes warpage tendency. This preliminary grinding action on the back surface creates a foundation that allows subsequent front surface polishing to proceed without requiring additional back surface polishing to control warpage.
Solution Approach 2:
The patent changes the surface roughness parameter of the back surface (C-face) to Sa≤1nm through precise grinding control. This parameter optimization ensures that the back surface has sufficient flatness to prevent excessive warpage during subsequent processing and device fabrication, eliminating the need for time-consuming back surface polishing while maintaining warpage control within acceptable limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach shortens the manufacturing lead time and reduces costs by minimizing the need for extensive polishing on the back surface while maintaining substrate quality, thereby enhancing the efficiency of SiC substrate production for power devices.
Implementation Method 1
a second grinding step of grinding the sliced SiC substrate on the side of the back surface such that the back surface has an arithmetic mean height Sa of 1 nm or less
Data Source
AI summary
A method of manufacturing a SiC substrate includes grinding a sliced SiC substrate on a side of its front surface on which a Si-face is exposed, grinding the sliced SiC substrate on a side of its back surface on which a C-face is exposed, such that the back surface has an arithmetic mean height Sa of 1 nm or less, and then polishing the sliced SiC substrate on the side of only the front surface and not on the side of the back surface. In a case where the side of the back surface is ground as described above, the SiC substrate can be prevented from being warped even if the side of the back surface is not polished. This can shorten the manufacturing lead time for the SiC substrate used for the manufacture of power devices or the like and can also reduce the manufacturing cost.