Polycrystalline SiC Substrate Grain Size Control for Warpage Reduction

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Solution Overview

Problem

Polycrystalline SiC substrates experience warpage due to internal stress, which hinders their practical application in high-voltage/high-power electronic devices and increases manufacturing costs, especially when attempting to reduce substrate thickness for lower electrical resistance.

Innovation Solution

A polycrystalline SiC substrate with a crystal grain size change rate of 0.43% or less and a radius of curvature of 142 m or more is developed, achieved through controlled chemical vapor deposition and sublimation methods, with surface roughness of 1 nm or less to enhance bonding strength and reduce residual stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the substrate thickness is reduced to lower electrical resistance, then the electrical resistance decreases, but the warpage increases due to residual stress

Engineering Contradiction:
Improveelectrical resistanceVSAvoidwarpage
Core Design Contradiction:
Loss of energyVSShape

Solution Approach 1:

The patent controls the crystal grain size change rate (a parameter) to be 0.43% or less across the substrate thickness, which fundamentally changes the stress distribution pattern and enables thin substrates to maintain flatness despite residual stress

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent performs preliminary control of crystal grain size uniformity during the CVD growth process itself, rather than attempting to correct warpage after substrate fabrication. This preliminary action prevents warpage from developing in the first place

Inventive Principle:
Principle #10Preliminary action

2Reliability

If chemical vapor deposition is used to grow polycrystalline SiC, then the substrate density increases and impurity concentration decreases, but internal stress is generated causing warpage

Engineering Contradiction:
Improvesubstrate qualityVSAvoidwarpage
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent identifies and controls the crystal grain size change rate as a critical parameter during CVD growth, maintaining it at 0.43% or less to prevent stress accumulation while preserving the high density and low impurity concentration benefits of CVD

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent establishes a feedback mechanism where the crystal grain size change rate is measured and used to adjust CVD process parameters, creating a closed-loop control system that prevents warpage while maintaining substrate quality

Inventive Principle:
Principle #23Feedback

3Reliability

If the improved Rayleigh method is used to grow SiC single crystal, then crystal quality improves and defect density decreases, but the manufacturing cost increases due to low growth rate and high processing cost

Engineering Contradiction:
Improvecrystal qualityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses polycrystalline SiC as a disposable support substrate that can be manufactured more cheaply than single crystal SiC, sacrificing the support substrate after bonding to retain the high-quality single crystal device layer

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent segments the substrate into two functional parts: a polycrystalline support substrate for mechanical strength and low-cost manufacturing, and a single crystal device layer for high performance, allowing each part to be optimized independently

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach effectively reduces warpage and improves bonding strength between the polycrystalline SiC substrate and single crystal SiC semiconductor layers, leading to improved fabrication yields and lower manufacturing costs for high-voltage/high-power electronic devices.

Implementation Method 1

Polycrystalline SiC substrates are formed by a method in which SiC is grown on a base material formed of, for example, carbon or the like by chemical vapor deposition (CVD)

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Implementation Method 2

an improved Rayleigh method has been developed in which sublimation recrystallization is performed using a SiC single crystal substrate as a seed crystal

Methodology Applied
Scientific EffectSublimation: Sublimation

Data Source

PatentUS10934634B2Polycrystalline SiC substrate and method for manufacturing same
Publication Date: 2021.03.02 SUMITOMO METAL MINING CO LTD
  • US10934634B2 patent drawing
  • US10934634B2 patent drawing
  • US10934634B2 patent drawing

AI summary

A support substrate 2 is a polycrystalline SiC substrate formed of polycrystalline SiC. Assuming that one of the two sides of the polycrystalline SiC substrate is a first side and that the other side is a second side, a substrate grain size change rate of the polycrystalline SiC substrate, which is a value obtained by dividing a difference between the average value of crystal grain sizes of the polycrystalline SiC on the first side and the average value of crystal grain sizes of the polycrystalline SiC on the second side by a thickness of the polycrystalline SiC substrate, is 0.43% or less. A radius of curvature of the polycrystalline SiC substrate is 142 m or more.