SiC Substrate Minority Carrier Lifetime Control
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Solution Overview
Problem
The manufacturing of silicon carbide substrates for semiconductor devices faces challenges in reducing defects and distortion, which affects yield and on-resistance variation, particularly in maintaining a low standard deviation of minority carrier lifetime near the substrate's perimeter.
Innovation Solution
A silicon carbide substrate with a majority carrier density of 1×10^17 cm^-3 or greater and a standard deviation of minority carrier lifetime of 0.7 ns or less, achieved through specific processing methods including μ-PCD analysis and carbon powder management to prevent carbon inclusions, enabling reduced on-resistance variation and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hot isostatic pressing is applied to reduce defects and distortion, then manufacturing yield is improved, but the standard deviation of minority carrier lifetime near the perimeter increases
Solution Approach 1:
The patent applies different processing conditions to different regions of the silicon carbide substrate. Specifically, the perimeter region (within 5mm from the outer perimeter) is treated differently from the central region, with the perimeter showing higher minority carrier lifetime standard deviation (1.0ns or more) while the center maintains lower standard deviation (0.7ns or less). This local differentiation resolves the contradiction by allowing yield improvement through hot isostatic pressing in the central region while accepting perimeter variations.
2Reliability
If carrier lifetime uniformity is improved across the substrate, then on-resistance variation decreases, but manufacturing complexity increases
Solution Approach 1:
The patent focuses control efforts on the central region of the substrate rather than attempting to uniformly optimize the entire surface. By setting the minority carrier lifetime standard deviation to 0.7ns or less specifically in the central area (excluding the 5mm perimeter zone), the patent achieves sufficient on-resistance uniformity for device performance while avoiding the excessive complexity of controlling the inherently variable perimeter regions.
3Manufacturing precision
If the substrate perimeter region is optimized for low minority carrier lifetime variation, then overall uniformity improves, but manufacturing cost increases
Solution Approach 1:
The patent divides the substrate into two distinct zones: a central region (excluding the 5mm perimeter) and a perimeter region. Each zone is evaluated and controlled independently with different specifications. The central region requires standard deviation of 0.7ns or less, while the perimeter region accepts 1.0ns or more. This segmentation allows cost-effective manufacturing by not expending excessive resources to optimize the perimeter region that contributes less to overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces on-resistance variation and improves yield in semiconductor device manufacturing by maintaining a low standard deviation of minority carrier lifetime, enhancing the quality and efficiency of silicon carbide substrates for applications like SBDs and MOSFETs.
Implementation Method 1
the standard deviation of minority carrier lifetime as obtained by μ-PCD analysis is 0.7 ns or less in the area other than the area within a distance of 5 mm from the outer perimeter of the main surface
Implementation Method 2
Technology has been developed that performs hot isostatic pressing to reduce defects and distortion in the manufacturing of silicon carbide substrates
Data Source
AI summary
A silicon carbide substrate whose majority carrier density is 1×1017 cm−3 or greater is such that a standard deviation of minority carrier lifetime as obtained by μ-PCD analysis is 0.7 ns or less in an area other than an area within a distance of 5 mm from an outer perimeter of a main surface.


