Silicon Carbide Substrate Ohmic Contact Fabrication
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Solution Overview
Problem
The challenge in fabricating silicon carbide semiconductor devices lies in forming ohmic contacts on fragile substrates with high contact resistance, which is exacerbated by the need for high annealing temperatures that conflict with the requirement to maintain low temperatures for transistor mobility and reduce substrate cracking and dust generation during roughening processes.
Innovation Solution
A method involving the formation of a thin first metal layer on the silicon carbide substrate, followed by dry-etching to create holes, and subsequent deposition of a second metal layer for ohmic contact, allowing for reduced annealing temperatures and eliminating the need for mechanical substrate roughening, thereby reducing contact resistance and preventing substrate damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the back face of the substrate is roughened by grinding to reduce contact resistance, then the contact resistance between back face metal and substrate is reduced, but dust is generated during substrate conveyance and yield is reduced
Solution Approach 1:
The patent replaces the mechanical grinding process with a chemical etching process using a wet etchant solution. This substitution eliminates mechanical contact that generates dust, while still achieving the desired surface roughening effect to reduce contact resistance. The chemical etching creates a textured surface through controlled material removal without the mechanical forces that cause substrate damage and dust generation.
Solution Approach 2:
The patent employs a liquid etchant solution delivered through a nozzle system to etch the substrate surface. The hydraulic delivery method allows precise control of the etching process, directing the chemical solution only where needed on the substrate surface, and enables easy removal of the etchant without generating dust, thereby maintaining high yield while achieving low contact resistance.
2Manufacturing precision
If high annealing temperature is applied to reduce contact resistance, then the contact resistance of back face metal is reduced, but the hydrogen terminal at the gate oxide interface is broken and device properties deteriorate
Solution Approach 1:
The patent changes the key parameter of annealing temperature from high (1000°C) to low (below 800°C, preferably 600-700°C). This parameter change allows the formation of ohmic contacts with sufficiently low contact resistance while preserving the hydrogen terminal structure at the gate oxide interface, thereby maintaining device properties such as mobility. The low temperature process achieves the desired electrical contact without the thermal energy that would break hydrogen bonds.
Solution Approach 2:
The patent performs preliminary surface roughening of the substrate back face before metal deposition. This preliminary action increases the effective contact area and improves wetting of the metal layer, which compensates for the lower annealing temperature. By preparing the surface in advance, the process achieves low contact resistance at reduced temperatures, preventing hydrogen terminal breakdown while still forming quality ohmic contacts.
3Manufacturing precision
If machine work is applied to the back face after device structure fabrication, then contact resistance is reduced, but pressure concentrates and substrate cracking and chipping occur
Solution Approach 1:
The patent performs the surface roughening action before metal layer deposition and device assembly, when the substrate is still accessible and can be handled appropriately. This preliminary preparation of the surface texture allows subsequent low-temperature metal annealing to achieve low contact resistance without requiring high-pressure mechanical work that would crack the substrate after device structure fabrication.
Solution Approach 2:
The patent replaces mechanical pressing or grinding operations with chemical etching to create surface texture. This substitution eliminates the concentrated mechanical pressure that causes substrate cracking and chipping, while still achieving the surface roughening needed for low contact resistance. The chemical process applies uniform stress through the liquid etchant rather than localized mechanical force.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance between the back face metal and the silicon carbide substrate at lower annealing temperatures, preventing substrate cracking and dust generation, thus enhancing the yield and performance of semiconductor devices.
Implementation Method 1
A first metal layer is formed on a back face of a silicon carbide substrate
Implementation Method 2
Many holes are formed on the back face of the silicon carbide substrate by dry-etching the back face of the silicon carbide substrate using the first metal layer as a mask therefor
Implementation Method 3
A second metal layer constituting an ohmic contact is formed on the first metal layer and the back face of the silicon carbide substrate including inner surfaces of the many holes
Implementation Method 4
the ohmic contact on the back face of the silicon carbide substrate can be formed at a low temperature
Data Source
AI summary
A first metal layer (3) is formed on a back face of a silicon carbide substrate (1) to a degree such that the first metal layer (3) does not fully cover the back face of the silicon carbide substrate. Many holes (4) are formed on the back face of the silicon carbide substrate (1) by dry-etching the back face of the silicon carbide substrate (1) using the first metal layer (3) as a mask therefor. A second metal layer constituting an ohmic contact is formed on the first metal layer (3) and the back face of the silicon carbide substrate (1) including inner surfaces of the many holes (4).

