SiC Substrate Ultra-High-Concentration Layer for Low Forward Resistance
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Solution Overview
Problem
Existing silicon carbide (SiC) substrates for vertical semiconductor devices have high forward resistance due to substrate and contact resistances, which hinder the reduction of substrate thickness and impurity concentration without compromising mechanical strength or introducing crystalline defects.
Innovation Solution
A semiconductor substrate with a silicon carbide structure comprising a bulk substrate, an ultra-high-concentration layer, a buffer layer, and an epitaxial layer, where the ultra-high-concentration layer is formed with a higher impurity concentration than the bulk substrate and epitaxial layer, and the substrate is thinned to reduce forward resistance while maintaining mechanical integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the substrate thickness is reduced to lower substrate resistance, then forward resistance decreases, but the substrate may crack during device fabrication process
Solution Approach 1:
The patent applies local quality by creating an ultra-high-concentration layer at the backside surface of the substrate with impurity concentration significantly higher than the bulk substrate. This localized high-concentration region reduces contact resistance at the electrode interface without requiring overall substrate thinning, thus maintaining mechanical strength while lowering forward resistance.
Solution Approach 2:
The patent changes the impurity concentration parameter locally at the backside surface by forming an ultra-high-concentration layer with impurity concentration of 1×10^19 to 1×10^21 atoms/cm³, while the bulk substrate maintains lower concentration (1×10^16 to 1×10^18 atoms/cm³). This parameter change reduces contact resistance without compromising substrate integrity.
2Object-affected harmful factors
If the impurity concentration at the backside surface is increased to reduce contact resistance, then forward resistance decreases, but the process becomes complex requiring ion implantation and high-temperature anneal
Solution Approach 1:
The patent applies preliminary action by forming the ultra-high-concentration layer at the backside surface before electrode formation. This pre-formed high-concentration layer is ready to receive the electrode, eliminating the need for subsequent ion implantation and high-temperature annealing processes that would be required if the layer were formed after electrode deposition.
Solution Approach 2:
The patent extracts the high-concentration layer formation step from the complex ion implantation and annealing process by forming the ultra-high-concentration layer epitaxially during substrate growth. This separates the concentration enhancement from the electrode formation process, simplifying the overall fabrication sequence.
3Object-affected harmful factors
If both substrate thickness is reduced and impurity concentration is increased, then forward resistance is minimized, but it has been impossible to achieve both simultaneously
Solution Approach 1:
The patent segments the substrate structure into distinct regions: a bulk substrate with moderate impurity concentration and an ultra-high-concentration layer at the backside surface. This segmentation allows each region to be optimized independently - the bulk for mechanical strength and the surface layer for low contact resistance - achieving both thinning and high concentration without manufacturing conflicts.
Solution Approach 2:
The patent creates a composite structure with two distinct impurity concentration zones within the same substrate. The bulk substrate and ultra-high-concentration layer function as composite regions with different electrical and mechanical properties, enabling simultaneous optimization of thickness and concentration that cannot be achieved in a homogeneous substrate.
Data Source
AI summary
A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher the an either the first impurity concentration or the third impurity concentration.