SiC Superjunction Drift Region Using Channeled Ion Implantation
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Solution Overview
Problem
Conventional methods for forming superjunction-type drift regions in silicon carbide power semiconductor devices face challenges such as breakdown voltage issues due to carrier tunneling and non-uniform dopant incorporation, particularly in silicon carbide and gallium nitride based materials, leading to increased fabrication time and cost.
Innovation Solution
A method involving high-energy channeled ion implantation along specific crystallographic directions to form p-type pillars in a mesa structure, with a doped mesa implant acting as a de-channeling screen to restrict the superjunction implant to the trenched region, allowing for charge balance and high blocking voltages without the need for epitaxial regrowth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ion implantation methods are used to form superjunction drift regions, then dopant can be introduced into the semiconductor material, but breakdown voltage is reduced due to carrier tunneling and non-uniform dopant incorporation
Solution Approach 1:
The patent changes the implantation parameters by using channeled ion implantation along specific crystallographic directions (e.g., <110> direction in silicon carbide). This directional implantation approach fundamentally alters how dopants are introduced, achieving uniform dopant incorporation at controlled depths while maintaining high blocking voltage capabilities by preventing carrier tunneling issues associated with conventional implantation methods
2Reliability
If high-energy channeled ion implantation is used to achieve uniform dopant incorporation and high blocking voltage, then fabrication time and process complexity increase
Solution Approach 1:
The patent performs preliminary actions by carefully preparing the semiconductor substrate with specific crystallographic orientation and surface preparation before implantation. The implantation process itself is designed as a single-step high-energy channeled implantation that achieves the desired superjunction structure without requiring multiple sequential implantation steps or subsequent epitaxial regrowth, thereby reducing overall fabrication time
3Reliability
If conventional superjunction formation methods are used, then charge balance can be achieved in the drift region, but epitaxial regrowth is required which increases fabrication complexity and cost
Solution Approach 1:
The patent extracts and eliminates the epitaxial regrowth step from the conventional superjunction formation process. By using high-energy channeled ion implantation, the method achieves complete dopant incorporation and charge balance directly in the implantation step, removing the need for subsequent high-temperature epitaxial regrowth processes and their associated complexity and cost
4Reliability
If the drift region is designed to block high voltages, then leakage current increases due to electric field crowding at the edges of the active region
Solution Approach 1:
The patent applies local quality by creating a superjunction structure with alternating n-type and p-type pillars in the drift region. This local alternation of conductivity types throughout the drift region, rather than a uniform structure, effectively distributes and reduces electric field crowding at the edges of the active region, thereby reducing leakage current while maintaining high voltage blocking capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces specific on-resistance and enhances the blocking voltage capabilities of silicon carbide JFET devices, achieving efficient charge balance and minimizing fabrication complexity and cost.
Implementation Method 1
A method involving high-energy channeled ion implantation along specific crystallographic directions to form p-type pillars in a mesa structure
Implementation Method 2
high-energy channeled ion implantation along specific crystallographic directions
Implementation Method 3
a doped mesa implant acting as a de-channeling screen to restrict the superjunction implant to the trenched region
Data Source
AI summary
A semiconductor device includes a substrate and an epitaxial structure on the substrate. The epitaxial structure includes a drift region and a mesa stripe on the drift region. The mesa stripe includes a channel region on the drift region, a source region on the channel region, and sidewall gate regions on opposite sides of the channel region. The channel region and the source region have a first conductivity type and the sidewall gate regions have a second conductivity type opposite the first conductivity type. The drift region includes a central pillar having the first conductivity type and outer pillars on opposite sides of the central pillar. The outer pillars have the first conductivity type, and the outer pillars and the central pillar form a superjunction structure in the drift region. Related methods are also disclosed.