SiC Superjunction MOSFET Pillar Arrangement for On-Resistance Reduction
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Solution Overview
Problem
The existing superjunction structure in semiconductor devices limits the reduction of on-resistance due to decreased channel density and increased channel resistance, particularly in high breakdown-voltage MOSFETs with SiC as the semiconductor material, where the density along the channel width is compromised by the complexity of pillar formation and trench alignment.
Innovation Solution
A semiconductor device with a superjunction layer featuring alternately aligned n-type and p-type pillars, where both first and second wells contribute to the current path, increasing the channel width density and reducing on-resistance by optimizing the width and arrangement of pillars and impurity regions, allowing for a higher density of MOS structures even with the superjunction structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a superjunction structure with alternately aligned p-type and n-type pillars is formed to reduce drift resistance, then withstand voltage is improved, but channel density decreases and channel resistance increases
Solution Approach 1:
The drift layer is segmented into alternating p-type and n-type pillars, creating multiple depletion regions that collectively provide high withstand voltage while maintaining current conduction paths through the n-type pillars. This segmentation allows the device to achieve both high voltage blocking capability and acceptable on-resistance by distributing the voltage stress across multiple junctions.
Solution Approach 2:
Different regions of the semiconductor structure are assigned different doping types and concentrations optimized for their specific functions: p-type pillars are optimized for voltage blocking with appropriate acceptor concentration, while n-type pillars are optimized for current conduction with higher donor concentration. This local optimization allows each region to contribute maximally to its intended function, resolving the trade-off between withstand voltage and channel resistance.
2Reliability
If the width of pillar structures is reduced to increase channel density, then on-resistance is reduced, but manufacturing precision becomes more difficult to achieve
Solution Approach 1:
The pillar structures are formed using preliminary patterning and etching steps that define the pillar dimensions before final device fabrication. By establishing the pillar width and spacing early in the manufacturing process through carefully controlled deposition and etching parameters, the design achieves optimal channel density while maintaining manufacturability through standard fabrication capabilities.
3Strength
If the depth of pillar structures is increased to achieve higher withstand voltage, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The superjunction structure utilizes the vertical dimension by forming deep alternating p-type and n-type pillars that extend through the drift layer. This vertical arrangement of dopant regions creates multiple horizontal depletion planes at different depths, achieving high breakdown voltage through the cumulative effect of multiple junctions rather than requiring a single complex structure. The dimensional approach simplifies the overall device design by using repeated vertical patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the on-resistance of the semiconductor device by enhancing the channel width density, thereby minimizing the channel resistance and maintaining high withstand voltage, even with the challenges posed by SiC as the semiconductor material.
Implementation Method 1
depletion layers expand also from pn-junction faces between the p-type pillars and the n-type pillar, aside from depletion layers that expand from pn-junction faces or metal joining faces that exist in the vicinity of the surfaces of semiconductor elements
Implementation Method 2
depletion layers expand also from pn-junction faces between the p-type pillars and the n-type pillar
Data Source
AI summary
A superjunction layer includes first pillars of a first conductivity type and second pillars of a second conductivity type. First wells are provided respectively on the second pillars to reach the first pillars and are of the second conductivity type. First impurity regions are provided respectively on the first wells and are of the first conductivity type. Second wells are provided respectively on the first pillars, spaced from the second pillars in a section of an active region that is perpendicular to a semiconductor layer, and are of the second conductivity type. Second impurity regions are provided respectively on the second wells and are of the first conductivity type.