SiC Switch-Back Engineered Substrate for Low-Defect Power MOSFETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving low defect densities in silicon carbide (SiC) substrates, leading to high manufacturing costs and reduced yield.
Innovation Solution
A process for forming a substantially defect-free silicon carbide switch-back engineered substrate involves creating a sacrificial, inverted pyramid patterned Si substrate, epitaxially growing SiC on it, and then bonding it with a defect-free SiC layer to produce a substrate with reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SiC is grown on Si substrate, then manufacturing cost is reduced and productivity is improved, but defect density increases due to lattice mismatch and thermal expansion differences
Solution Approach 1:
The substrate structure is segmented into multiple functional layers: a Si substrate providing mechanical support, a buffer layer reducing stress, and a SiC layer providing the desired semiconductor properties. This segmentation allows each layer to optimize its function while mitigating the harmful effects of direct Si-SiC bonding.
Solution Approach 2:
A buffer layer is introduced as an intermediary between the Si substrate and the SiC layer. This buffer layer acts as a mediator that reduces the stress and dislocation transmission from the Si substrate to the SiC layer, thereby reducing defect density while maintaining the cost advantages of Si substrate usage.
2Reliability
If high temperature anneal is performed on SiC, then material properties are improved, but manufacturing cost increases due to specialized equipment requirements
Solution Approach 1:
The buffer layer is prepared in advance on the Si substrate before SiC growth. This preliminary action reduces stress during subsequent high-temperature processing, enabling standard CMOS fabrication equipment to handle the materials without requiring specialized high-cost equipment for the entire process.
Solution Approach 2:
The process utilizes standard CMOS temperature ranges rather than requiring extreme high-temperature annealing. By optimizing the buffer layer composition and structure, the desired material properties are achieved within the capabilities of existing CMOS fabrication equipment, reducing manufacturing costs.
3Reliability
If defect reduction techniques are applied to SiC substrate, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The buffer layer structure enables the SiC layer to self-limit defect propagation. The buffer layer absorbs and redistributes stress, allowing the SiC layer to grow with reduced defect density using standard growth techniques, without requiring additional costly defect reduction processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor substrate with significantly reduced defect density, enabling the production of high-breakdown voltage power MOSFETs with improved reliability and lower manufacturing costs.
Implementation Method 1
epitaxially growing SiC on it
Implementation Method 2
bonding it with a defect-free SiC layer
Data Source
AI summary
A semiconductor device has a first substrate and a first semiconductor layer formed over the first substrate. A second substrate is disposed over a surface of the first semiconductor layer opposite the first substrate. The first semiconductor layer and second semiconductor layer can be silicon carbide or cubic silicon carbide. The first substrate and a portion of the first semiconductor layer are removed to reduce defects in the first semiconductor layer. A second semiconductor layer is formed over a remaining portion of the first semiconductor layer. A third semiconductor layer is disposed over the second semiconductor layer. The third semiconductor layer can be silicon. The third semiconductor layer can be disposed over the second semiconductor layer by direct wafer bonding. An electrical component is formed within the third semiconductor layer. The electrical component can be a power MOSFET, IGBT, CTIGBT, diode, and thyristor.